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AVR64DB64T-E

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleravr64db64t-efactory-2.0.0extractor-text

Verified AVR64DB64T-E

by Ray · last 9 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

9 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR64DB64T-E · VQFN-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 665-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-58ncotbg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr64db64t-e.kicad_sym✓ avr64db64t-e.kicad_mod✓ avr64db64t-e.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers avr64db64t-e: viewers · Ray
avr64db64t-e-etched.glb Publish 0.1.0 · Ray
avr64db64t-e-etched.step avr64db64t-e: factory component page (tier=mfr) · Ray
avr64db64t-e-hero.glb avr64db64t-e: hero GLB from the etched model (keeps the MPN mark) · Ray
avr64db64t-e-hero.overlay.json Publish 0.1.0 · Ray
avr64db64t-e.glb Publish 0.1.0 · Ray
avr64db64t-e.kicad_mod Publish 0.1.0 · Ray
avr64db64t-e.kicad_sym Publish 0.1.0 · Ray
avr64db64t-e.lbr Publish 0.1.0 · Ray
avr64db64t-e.step Publish 0.1.0 · Ray
package.json Publish 0.1.1 · Ray
page.json Publish 0.1.1 · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray

AVR64DB64T-E

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64(9x9)

AVR64DB64T-E from Microchip Tech, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional PORTA pin 3 general-purpose I/O with TWI Fm+ capability (TWI0 SCL host/client), USART0 XDIR, TCA0 WO3 and LUT0 OUT alternates.
2 PA4 bidirectional PORTA pin 4 general-purpose I/O with USART0 TxD and SPI0 MOSI (alternate positions), TCA0 WO4 and TCD0 WOA.
3 PA5 bidirectional PORTA pin 5 general-purpose I/O with USART0 RxD and SPI0 MISO (alternate positions), TCA0 WO5 and TCD0 WOB.
4 PA6 bidirectional PORTA pin 6 general-purpose I/O with USART0 XCK and SPI0 SCK (alternate positions), TCD0 WOC and LUT0 OUT alternate.
5 PA7 bidirectional PORTA pin 7 general-purpose I/O with CLKOUT, default AC0/AC1/AC2 OUT and ZCD0/1/2 OUT, SPI0 SS, TCD0 WOD and EVOUTA alternate.
6 VDD power_in Positive supply powering I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD and AVDD pins.
7 GND power_in Ground, common to the VDD, AVDD and VDDIO2 domains.
8 PB0 bidirectional PORTB pin 0 general-purpose I/O with USART3 TxD, TCA1 WO0 (TCA0 WO0 alternate) and LUT4 IN0.
9 PB1 bidirectional PORTB pin 1 general-purpose I/O with USART3 RxD, TCA1 WO1 (TCA0 WO1 alternate) and LUT4 IN1.
10 PB2 bidirectional PORTB pin 2 general-purpose I/O with USART3 XCK, TWI1 SDA (host/client), TCA1 WO2, EVOUTB and LUT4 IN2.
11 PB3 bidirectional PORTB pin 3 general-purpose I/O with USART3 XDIR, TWI1 SCL (host/client), TCA1 WO3 and LUT4 OUT.
12 PB4 bidirectional PORTB pin 4 general-purpose I/O with USART3 TxD and SPI1 MOSI (alternate), TCA1 WO4 and TCB2 WO.
13 PB5 bidirectional PORTB pin 5 general-purpose I/O with USART3 RxD and SPI1 MISO (alternate), TCA1 WO5 and TCB3 WO.
14 PB6 bidirectional PORTB pin 6 general-purpose I/O with USART3 XCK, SPI1 SCK, TWI1 SDA (client only), TCD0 WOC and LUT4 OUT (alternate positions).
15 PB7 bidirectional PORTB pin 7 general-purpose I/O with USART3 XDIR, SPI1 SS, TWI1 SCL (client only), TCD0 WOD and EVOUTB (alternate positions).
16 PC0 bidirectional PORTC pin 0 general-purpose I/O powered from VDDIO2 (MVIO) with USART1 TxD, SPI1 MOSI, TCB2 WO and LUT1 IN0.
17 PC1 bidirectional PORTC pin 1 general-purpose I/O powered from VDDIO2 (MVIO) with USART1 RxD, SPI1 MISO, TCB3 WO and LUT1 IN1.
18 PC2 bidirectional PORTC pin 2 general-purpose I/O powered from VDDIO2 (MVIO) with TWI Fm+ capability, USART1 XCK, SPI1 SCK, EVOUTC and LUT1 IN2.
19 PC3 bidirectional PORTC pin 3 general-purpose I/O powered from VDDIO2 (MVIO) with TWI Fm+ capability, USART1 XDIR, SPI1 SS and LUT1 OUT.
20 VDDIO2 power_in Supply for the MVIO-capable I/O pins (PORTC), which can be at a different voltage from VDD in dual-supply mode; must be tied to VDD in single-supply mode.
21 GND power_in Ground, common to the VDD, AVDD and VDDIO2 domains.
22 PC4 bidirectional PORTC pin 4 general-purpose I/O powered from VDDIO2 (MVIO) with USART1 TxD and SPI1 MOSI (alternate), TCA0 WO4 and TCA1 WO0.
23 PC5 bidirectional PORTC pin 5 general-purpose I/O powered from VDDIO2 (MVIO) with USART1 RxD and SPI1 MISO (alternate), TCA0 WO5 and TCA1 WO1.
24 PC6 bidirectional PORTC pin 6 general-purpose I/O powered from VDDIO2 (MVIO) with AC0/1/2 OUT, USART1 XCK, SPI1 SCK, TWI0 SDA (client only) and LUT1 OUT (alternate positions).
25 PC7 bidirectional PORTC pin 7 general-purpose I/O powered from VDDIO2 (MVIO) with AC0/1/2 OUT, USART1 XDIR, SPI1 SS, TWI0 SCL (client only) and EVOUTC (alternate positions).
26 PD0 bidirectional PORTD pin 0 general-purpose I/O with ADC0 input AIN0, negative inputs AINN1 of AC0/AC1/AC2, TCA0 WO0 and LUT2 IN0.
27 PD1 bidirectional PORTD pin 1 general-purpose I/O with ADC0 input AIN1, OPAMP0 INP, ZCD0 ZCIN, TCA0 WO1 and LUT2 IN1.
28 PD2 bidirectional PORTD pin 2 general-purpose I/O with ADC0 input AIN2, positive inputs AINP0 of AC0/AC1/AC2, OPAMP0 OUT, EVOUTD and LUT2 IN2.
29 PD3 bidirectional PORTD pin 3 general-purpose I/O with ADC0 input AIN3, AC0 AINN0, AC1 AINP1, OPAMP0 INN and LUT2 OUT.
30 PD4 bidirectional PORTD pin 4 general-purpose I/O with ADC0 input AIN4, AC1 AINP2, AC2 AINP1, OPAMP1 INP and TCA0 WO4.
31 PD5 bidirectional PORTD pin 5 general-purpose I/O with ADC0 input AIN5, AC1 AINN0, OPAMP1 OUT and TCA0 WO5.
32 PD6 bidirectional PORTD pin 6 general-purpose I/O with ADC0 input AIN6, AINP3 of AC0/AC1/AC2, DAC0 OUT and LUT2 OUT (alternate).
33 PD7 bidirectional PORTD pin 7 general-purpose I/O with external voltage reference input VREFA, ADC0 input AIN7, AINN2 comparator inputs, OPAMP1 INN and EVOUTD (alternate).
34 AVDD power_in Supply for I/O lines, XOSC32K and the analog peripherals; internally connected to VDD and must be at the same voltage.
35 AGND power_in Analog ground pin, shown as GND in the pinout and common to the VDD, AVDD and VDDIO2 domains.
36 PE0 bidirectional PORTE pin 0 general-purpose I/O with ADC0 input AIN8, AC0 AINP1, USART4 TxD, SPI0 MOSI (alternate) and TCA0 WO0 (alternate).
37 PE1 bidirectional PORTE pin 1 general-purpose I/O with ADC0 input AIN9, AC2 AINP2, OPAMP2 INP, USART4 RxD and SPI0 MISO (alternate).
38 PE2 bidirectional PORTE pin 2 general-purpose I/O with ADC0 input AIN10, AC0 AINP2, OPAMP2 OUT, USART4 XCK, EVOUTE.
39 PE3 bidirectional PORTE pin 3 general-purpose I/O with ADC0 input AIN11, OPAMP2 INN, ZCD1 ZCIN, USART4 XDIR and SPI0 SS (alternate).
40 PE4 bidirectional PORTE pin 4 general-purpose I/O with ADC0 input AIN12, USART4 TxD (alternate) and TCA0 WO4 / TCA1 WO0 (alternate).
41 PE5 bidirectional PORTE pin 5 general-purpose I/O with ADC0 input AIN13, USART4 RxD (alternate) and TCA0 WO5 / TCA1 WO1 (alternate).
42 PE6 bidirectional PORTE pin 6 general-purpose I/O with ADC0 input AIN14, USART4 XCK (alternate) and TCA1 WO2 (alternate).
43 PE7 bidirectional PORTE pin 7 general-purpose I/O with ADC0 input AIN15, ZCD2 ZCIN, USART4 XDIR (alternate) and EVOUTE (alternate).
44 PF0 bidirectional PORTF pin 0 general-purpose I/O, also XTAL32K1 for the external 32.768 kHz crystal; ADC0 input AIN16 (not usable as negative differential input), USART2 TxD and LUT3 IN0.
45 PF1 bidirectional PORTF pin 1 general-purpose I/O, also XTAL32K2 for the external 32.768 kHz crystal; ADC0 input AIN17 (not usable as negative differential input), USART2 RxD and LUT3 IN1.
46 PF2 bidirectional PORTF pin 2 general-purpose I/O with TWI Fm+ capability, ADC0 input AIN18 (not usable as negative differential input), USART2 XCK, TWI1 SDA, EVOUTF and LUT3 IN2.
47 PF3 bidirectional PORTF pin 3 general-purpose I/O with TWI Fm+ capability, ADC0 input AIN19 (not usable as negative differential input), USART2 XDIR, TWI1 SCL and LUT3 OUT.
48 PF4 bidirectional PORTF pin 4 general-purpose I/O with ADC0 input AIN20 (not usable as negative differential input), USART2 TxD (alternate) and TCB0 WO (alternate).
49 PF5 bidirectional PORTF pin 5 general-purpose I/O with ADC0 input AIN21 (not usable as negative differential input), USART2 RxD (alternate) and TCB1 WO (alternate).
50 PF6 (RESET) input Input-only pin PF6 that serves as the external RESET when enabled by the RSTPINCFG fuse (pull-up enabled on PF6); the pin is held low to keep the device in reset.
51 UPDI bidirectional Dedicated Unified Program and Debug Interface pin using half-duplex asynchronous UART communication for programming and debugging.
52 PG0 bidirectional PORTG pin 0 general-purpose I/O with USART5 TxD, TCA0 WO0 / TCA1 WO0 (alternate) and LUT5 IN0.
53 PG1 bidirectional PORTG pin 1 general-purpose I/O with USART5 RxD, TCA0 WO1 / TCA1 WO1 (alternate) and LUT5 IN1.
54 PG2 bidirectional PORTG pin 2 general-purpose I/O with USART5 XCK, TCA0 WO2 / TCA1 WO2 (alternate), EVOUTG and LUT5 IN2.
55 PG3 bidirectional PORTG pin 3 general-purpose I/O with USART5 XDIR, TCA0 WO3 / TCA1 WO3 (alternate), TCB4 WO and LUT5 OUT.
56 VDD power_in Positive supply powering I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD and AVDD pins.
57 GND power_in Ground, common to the VDD, AVDD and VDDIO2 domains.
58 PG4 bidirectional PORTG pin 4 general-purpose I/O with USART5 TxD and SPI0 MOSI (alternate), TCA0 WO4 / TCA1 WO4 (alternate) and TCD0 WOA (alternate).
59 PG5 bidirectional PORTG pin 5 general-purpose I/O with USART5 RxD and SPI0 MISO (alternate), TCA0 WO5 / TCA1 WO5 (alternate) and TCD0 WOB (alternate).
60 PG6 bidirectional PORTG pin 6 general-purpose I/O with USART5 XCK and SPI0 SCK (alternate), TCD0 WOC and LUT5 OUT (alternate).
61 PG7 bidirectional PORTG pin 7 general-purpose I/O with USART5 XDIR and SPI0 SS (alternate), TCD0 WOD and EVOUTG (alternate).
62 PA0 bidirectional PORTA pin 0 general-purpose I/O, also XTALHF1 for the external high-frequency crystal or EXTCLK input, with USART0 TxD, TCA0 WO0 and LUT0 IN0.
63 PA1 bidirectional PORTA pin 1 general-purpose I/O, also XTALHF2 for the external high-frequency crystal, with USART0 RxD, TCA0 WO1 and LUT0 IN1.
64 PA2 bidirectional PORTA pin 2 general-purpose I/O with TWI Fm+ capability (TWI0 SDA host/client), USART0 XCK, TCA0 WO2, TCB0 WO, EVOUTA and LUT0 IN2.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-64(9x9)
Category Single Chip Microcomputer/Microcontroller
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 1.8 5.5 V Ordering information row AVR64DB64T-E/MR (QFN 64, Tape & Reel, -40°C to +125°C) 634

CAD (KiCad official)

  • Symbol: AVR64DB64T-E
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: avr64db64t-e-etched.step / avr64db64t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr64db64t-e.step / avr64db64t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (665 pp, sha256 adfeb5005d481e53, retrieved 2026-11-09, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF