component
AVR64DB48T-I
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AVR64DB48T-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-48(6x6)
AVR64DB48T-I from Microchip Tech, in a VQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA5 | bidirectional | General-purpose I/O PA5 with USART0 RxD (alternate), SPI0 MISO and TCA0 WO5 functions. |
| 2 | PA6 | bidirectional | General-purpose I/O PA6 with USART0 XCK (alternate), SPI0 SCK, TCD0 WOC and CCL LUT0 OUT (alternate). |
| 3 | PA7 | bidirectional | General-purpose I/O PA7 with CLKOUT, AC0/1/2 OUT, ZCD OUT, SPI0 SS, TCD0 WOD and EVOUTA (alternate). |
| 4 | PB0 | bidirectional | General-purpose I/O PB0 with USART3 TxD, TCA0/TCA1 WO0 and CCL LUT4 IN0. |
| 5 | PB1 | bidirectional | General-purpose I/O PB1 with USART3 RxD, TCA0/TCA1 WO1 and CCL LUT4 IN1. |
| 6 | PB2 | bidirectional | General-purpose I/O PB2 with USART3 XCK, TWI1 SDA (host/client), TCA WO2, EVOUTB and CCL LUT4 IN2. |
| 7 | PB3 | bidirectional | General-purpose I/O PB3 with USART3 XDIR, TWI1 SCL (host/client), TCA WO3 and CCL LUT4 OUT. |
| 8 | PB4 | bidirectional | General-purpose I/O PB4 with USART3 TxD (alternate), SPI1 MOSI (alternate), TCA WO4, TCB2 WO and TCD0 WOA (alternate). |
| 9 | PB5 | bidirectional | General-purpose I/O PB5 with USART3 RxD (alternate), SPI1 MISO (alternate), TCA WO5, TCB3 WO and TCD0 WOB (alternate). |
| 10 | PC0 | bidirectional | General-purpose I/O PC0 on the VDDIO2 (MVIO) domain with USART1 TxD, SPI1 MOSI, TCB2 WO and CCL LUT1 IN0. |
| 11 | PC1 | bidirectional | General-purpose I/O PC1 on the VDDIO2 (MVIO) domain with USART1 RxD, SPI1 MISO, TCB3 WO (alternate) and CCL LUT1 IN1. |
| 12 | PC2 | bidirectional | General-purpose I/O PC2 on the VDDIO2 (MVIO) domain with TWI Fm+ capability, USART1 XCK, SPI1 SCK, EVOUTC and CCL LUT1 IN2. |
| 13 | PC3 | bidirectional | General-purpose I/O PC3 on the VDDIO2 (MVIO) domain with TWI Fm+ capability, USART1 XDIR, SPI1 SS and CCL LUT1 OUT. |
| 14 | VDDIO2 | power_in | Supply for the multi-voltage I/O pins (port C); connect to VDD in single-supply mode or to a separate supply in dual-supply mode. |
| 15 | GND | power_in | Ground, common to VDD, AVDD and VDDIO2. |
| 16 | PC4 | bidirectional | General-purpose I/O PC4 on the VDDIO2 (MVIO) domain with alternate USART1 TxD, SPI1 MOSI and TCA0/TCB WO outputs. |
| 17 | PC5 | bidirectional | General-purpose I/O PC5 on the VDDIO2 (MVIO) domain with alternate USART1 RxD, SPI1 MISO and TCA0/TCB WO outputs. |
| 18 | PC6 | bidirectional | General-purpose I/O PC6 on the VDDIO2 (MVIO) domain with alternate AC OUT, USART1 XCK, SPI1 SCK, TWI0 SDA (client) and CCL LUT1 OUT. |
| 19 | PC7 | bidirectional | General-purpose I/O PC7 on the VDDIO2 (MVIO) domain with alternate AC OUT, USART1 XDIR, SPI1 SS, TWI0 SCL (client) and EVOUTC. |
| 20 | PD0 | bidirectional | General-purpose I/O PD0 with ADC0 AIN0, AC AINN1, TCA0 WO0 (alternate) and CCL LUT2 IN0. |
| 21 | PD1 | bidirectional | General-purpose I/O PD1 with ADC0 AIN1, OPAMP OP0 INP, ZCD0 ZCIN, TCA0 WO1 (alternate) and CCL LUT2 IN1. |
| 22 | PD2 | bidirectional | General-purpose I/O PD2 with ADC0 AIN2, AC AINP0, OPAMP OP0 OUT, EVOUTD and CCL LUT2 IN2. |
| 23 | PD3 | bidirectional | General-purpose I/O PD3 with ADC0 AIN3, AC AINN0/AINP1, OPAMP OP0 INN and CCL LUT2 OUT. |
| 24 | PD4 | bidirectional | General-purpose I/O PD4 with ADC0 AIN4, AC AINP2/AINP1, OPAMP OP1 INP and TCA0 WO4 (alternate). |
| 25 | PD5 | bidirectional | General-purpose I/O PD5 with ADC0 AIN5, AC1 AINN0, OPAMP OP1 OUT and TCA0 WO5 (alternate). |
| 26 | PD6 | bidirectional | General-purpose I/O PD6 with ADC0 AIN6, AC AINP3, DAC0 OUT and CCL LUT2 OUT (alternate). |
| 27 | PD7 | bidirectional | General-purpose I/O PD7 with VREFA external reference input, ADC0 AIN7, AC AINN2, OPAMP OP1 INN and EVOUTD (alternate). |
| 28 | AVDD | power_in | Analog supply powering analog peripherals, XOSC32K and I/O lines; internally connected to VDD and must be at the same voltage. |
| 29 | GND | power_in | Analog ground (AGND), common to VDD, AVDD and VDDIO2 ground. |
| 30 | PE0 | bidirectional | General-purpose I/O PE0 with ADC0 AIN8, AC0 AINP1, USART4 TxD and TCA0 WO0 (alternate). |
| 31 | PE1 | bidirectional | General-purpose I/O PE1 with ADC0 AIN9, AC AINP2, OPAMP OP2 INP and USART4 RxD. |
| 32 | PE2 | bidirectional | General-purpose I/O PE2 with ADC0 AIN10, AC0 AINP2, OPAMP OP2 OUT, USART4 XCK and EVOUTE. |
| 33 | PE3 | bidirectional | General-purpose I/O PE3 with ADC0 AIN11, OPAMP OP2 INN, ZCD1 ZCIN and USART4 XDIR. |
| 34 | PF0 | bidirectional | General-purpose I/O PF0 also used as XTAL32K1 (32.768 kHz crystal), with ADC0 AIN16 (not usable as differential negative input), USART2 TxD and CCL LUT3 IN0. |
| 35 | PF1 | bidirectional | General-purpose I/O PF1 also used as XTAL32K2 (32.768 kHz crystal), with ADC0 AIN17 (not usable as differential negative input), USART2 RxD and CCL LUT3 IN1. |
| 36 | PF2 | bidirectional | General-purpose I/O PF2 with TWI Fm+ capability, ADC0 AIN18 (not usable as differential negative input), USART2 XCK, TWI1 SDA, EVOUTF and CCL LUT3 IN2. |
| 37 | PF3 | bidirectional | General-purpose I/O PF3 with TWI Fm+ capability, ADC0 AIN19 (not usable as differential negative input), USART2 XDIR, TWI1 SCL and CCL LUT3 OUT. |
| 38 | PF4 | bidirectional | General-purpose I/O PF4 with ADC0 AIN20 (not usable as differential negative input), alternate USART2 TxD, TCA0 WO4 and TCB0 WO. |
| 39 | PF5 | bidirectional | General-purpose I/O PF5 with ADC0 AIN21 (not usable as differential negative input), alternate USART2 RxD, TCA0 WO5 and TCB1 WO. |
| 40 | PF6 | input | Input-only pin PF6, used as the external RESET input when enabled by the RSTPINCFG fuse (pull-up enabled on PF6). |
| 41 | UPDI | bidirectional | Unified Program and Debug Interface pin for one-wire half-duplex UART programming and debugging; dedicated pin with no other function. |
| 42 | VDD | power_in | Digital supply powering I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD and AVDD pins. |
| 43 | GND | power_in | Ground, common to VDD, AVDD and VDDIO2. |
| 44 | PA0 | bidirectional | General-purpose I/O PA0 also used as XTALHF1 crystal pin or EXTCLK input, with USART0 TxD, TCA0 WO0 and CCL LUT0 IN0. |
| 45 | PA1 | bidirectional | General-purpose I/O PA1 also used as XTALHF2 crystal pin, with USART0 RxD, TCA0 WO1 and CCL LUT0 IN1. |
| 46 | PA2 | bidirectional | General-purpose I/O PA2 with TWI Fm+ capability, USART0 XCK, TWI0 SDA (host/client), TCA0 WO2, TCB WO and EVOUTA. |
| 47 | PA3 | bidirectional | General-purpose I/O PA3 with TWI Fm+ capability, USART0 XDIR, TWI0 SCL (host/client), TCA0 WO3, TCB1 WO and CCL LUT0 OUT. |
| 48 | PA4 | bidirectional | General-purpose I/O PA4 with USART0 TxD (alternate), SPI0 MOSI, TCA0 WO4 and TCD0 WOA. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-48(6x6) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 1.8 | 5.5 | V | Supply Voltage per ordering table | 633 | |
| Operating temperature range (Industrial) | -40 | 85 | °C | I = -40°C to +85°C (Industrial) | 634 | ||
| CPU clock speed | 24 | MHz | AVR CPU clock speeds up to 24 MHz | 1 | |||
| PLL input frequency | 16 | MHz | Minimum input frequency of the PLL | 96 | |||
| PLL output frequency | 48 | MHz | Maximum output frequency | 96 | |||
| External clock frequency on XTALHF1 | 32 | MHz | External clock running at up to 32 MHz connected to XTALHF1 | 96 |
CAD (KiCad official)
- Symbol:
AVR64DB48T-I - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm - 3D model: VQFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
avr64db48t-i-etched.step/avr64db48t-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);avr64db48t-i.step/avr64db48t-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (665 pp, sha256
adfeb5005d481e53, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AVR64DB48T-I
**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-48(6x6)
AVR64DB48T-I from Microchip Tech, in a VQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA5 | bidirectional | General-purpose I/O PA5 with USART0 RxD (alternate), SPI0 MISO and TCA0 WO5 functions. |
| 2 | PA6 | bidirectional | General-purpose I/O PA6 with USART0 XCK (alternate), SPI0 SCK, TCD0 WOC and CCL LUT0 OUT (alternate). |
| 3 | PA7 | bidirectional | General-purpose I/O PA7 with CLKOUT, AC0/1/2 OUT, ZCD OUT, SPI0 SS, TCD0 WOD and EVOUTA (alternate). |
| 4 | PB0 | bidirectional | General-purpose I/O PB0 with USART3 TxD, TCA0/TCA1 WO0 and CCL LUT4 IN0. |
| 5 | PB1 | bidirectional | General-purpose I/O PB1 with USART3 RxD, TCA0/TCA1 WO1 and CCL LUT4 IN1. |
| 6 | PB2 | bidirectional | General-purpose I/O PB2 with USART3 XCK, TWI1 SDA (host/client), TCA WO2, EVOUTB and CCL LUT4 IN2. |
| 7 | PB3 | bidirectional | General-purpose I/O PB3 with USART3 XDIR, TWI1 SCL (host/client), TCA WO3 and CCL LUT4 OUT. |
| 8 | PB4 | bidirectional | General-purpose I/O PB4 with USART3 TxD (alternate), SPI1 MOSI (alternate), TCA WO4, TCB2 WO and TCD0 WOA (alternate). |
| 9 | PB5 | bidirectional | General-purpose I/O PB5 with USART3 RxD (alternate), SPI1 MISO (alternate), TCA WO5, TCB3 WO and TCD0 WOB (alternate). |
| 10 | PC0 | bidirectional | General-purpose I/O PC0 on the VDDIO2 (MVIO) domain with USART1 TxD, SPI1 MOSI, TCB2 WO and CCL LUT1 IN0. |
| 11 | PC1 | bidirectional | General-purpose I/O PC1 on the VDDIO2 (MVIO) domain with USART1 RxD, SPI1 MISO, TCB3 WO (alternate) and CCL LUT1 IN1. |
| 12 | PC2 | bidirectional | General-purpose I/O PC2 on the VDDIO2 (MVIO) domain with TWI Fm+ capability, USART1 XCK, SPI1 SCK, EVOUTC and CCL LUT1 IN2. |
| 13 | PC3 | bidirectional | General-purpose I/O PC3 on the VDDIO2 (MVIO) domain with TWI Fm+ capability, USART1 XDIR, SPI1 SS and CCL LUT1 OUT. |
| 14 | VDDIO2 | power_in | Supply for the multi-voltage I/O pins (port C); connect to VDD in single-supply mode or to a separate supply in dual-supply mode. |
| 15 | GND | power_in | Ground, common to VDD, AVDD and VDDIO2. |
| 16 | PC4 | bidirectional | General-purpose I/O PC4 on the VDDIO2 (MVIO) domain with alternate USART1 TxD, SPI1 MOSI and TCA0/TCB WO outputs. |
| 17 | PC5 | bidirectional | General-purpose I/O PC5 on the VDDIO2 (MVIO) domain with alternate USART1 RxD, SPI1 MISO and TCA0/TCB WO outputs. |
| 18 | PC6 | bidirectional | General-purpose I/O PC6 on the VDDIO2 (MVIO) domain with alternate AC OUT, USART1 XCK, SPI1 SCK, TWI0 SDA (client) and CCL LUT1 OUT. |
| 19 | PC7 | bidirectional | General-purpose I/O PC7 on the VDDIO2 (MVIO) domain with alternate AC OUT, USART1 XDIR, SPI1 SS, TWI0 SCL (client) and EVOUTC. |
| 20 | PD0 | bidirectional | General-purpose I/O PD0 with ADC0 AIN0, AC AINN1, TCA0 WO0 (alternate) and CCL LUT2 IN0. |
| 21 | PD1 | bidirectional | General-purpose I/O PD1 with ADC0 AIN1, OPAMP OP0 INP, ZCD0 ZCIN, TCA0 WO1 (alternate) and CCL LUT2 IN1. |
| 22 | PD2 | bidirectional | General-purpose I/O PD2 with ADC0 AIN2, AC AINP0, OPAMP OP0 OUT, EVOUTD and CCL LUT2 IN2. |
| 23 | PD3 | bidirectional | General-purpose I/O PD3 with ADC0 AIN3, AC AINN0/AINP1, OPAMP OP0 INN and CCL LUT2 OUT. |
| 24 | PD4 | bidirectional | General-purpose I/O PD4 with ADC0 AIN4, AC AINP2/AINP1, OPAMP OP1 INP and TCA0 WO4 (alternate). |
| 25 | PD5 | bidirectional | General-purpose I/O PD5 with ADC0 AIN5, AC1 AINN0, OPAMP OP1 OUT and TCA0 WO5 (alternate). |
| 26 | PD6 | bidirectional | General-purpose I/O PD6 with ADC0 AIN6, AC AINP3, DAC0 OUT and CCL LUT2 OUT (alternate). |
| 27 | PD7 | bidirectional | General-purpose I/O PD7 with VREFA external reference input, ADC0 AIN7, AC AINN2, OPAMP OP1 INN and EVOUTD (alternate). |
| 28 | AVDD | power_in | Analog supply powering analog peripherals, XOSC32K and I/O lines; internally connected to VDD and must be at the same voltage. |
| 29 | GND | power_in | Analog ground (AGND), common to VDD, AVDD and VDDIO2 ground. |
| 30 | PE0 | bidirectional | General-purpose I/O PE0 with ADC0 AIN8, AC0 AINP1, USART4 TxD and TCA0 WO0 (alternate). |
| 31 | PE1 | bidirectional | General-purpose I/O PE1 with ADC0 AIN9, AC AINP2, OPAMP OP2 INP and USART4 RxD. |
| 32 | PE2 | bidirectional | General-purpose I/O PE2 with ADC0 AIN10, AC0 AINP2, OPAMP OP2 OUT, USART4 XCK and EVOUTE. |
| 33 | PE3 | bidirectional | General-purpose I/O PE3 with ADC0 AIN11, OPAMP OP2 INN, ZCD1 ZCIN and USART4 XDIR. |
| 34 | PF0 | bidirectional | General-purpose I/O PF0 also used as XTAL32K1 (32.768 kHz crystal), with ADC0 AIN16 (not usable as differential negative input), USART2 TxD and CCL LUT3 IN0. |
| 35 | PF1 | bidirectional | General-purpose I/O PF1 also used as XTAL32K2 (32.768 kHz crystal), with ADC0 AIN17 (not usable as differential negative input), USART2 RxD and CCL LUT3 IN1. |
| 36 | PF2 | bidirectional | General-purpose I/O PF2 with TWI Fm+ capability, ADC0 AIN18 (not usable as differential negative input), USART2 XCK, TWI1 SDA, EVOUTF and CCL LUT3 IN2. |
| 37 | PF3 | bidirectional | General-purpose I/O PF3 with TWI Fm+ capability, ADC0 AIN19 (not usable as differential negative input), USART2 XDIR, TWI1 SCL and CCL LUT3 OUT. |
| 38 | PF4 | bidirectional | General-purpose I/O PF4 with ADC0 AIN20 (not usable as differential negative input), alternate USART2 TxD, TCA0 WO4 and TCB0 WO. |
| 39 | PF5 | bidirectional | General-purpose I/O PF5 with ADC0 AIN21 (not usable as differential negative input), alternate USART2 RxD, TCA0 WO5 and TCB1 WO. |
| 40 | PF6 | input | Input-only pin PF6, used as the external RESET input when enabled by the RSTPINCFG fuse (pull-up enabled on PF6). |
| 41 | UPDI | bidirectional | Unified Program and Debug Interface pin for one-wire half-duplex UART programming and debugging; dedicated pin with no other function. |
| 42 | VDD | power_in | Digital supply powering I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD and AVDD pins. |
| 43 | GND | power_in | Ground, common to VDD, AVDD and VDDIO2. |
| 44 | PA0 | bidirectional | General-purpose I/O PA0 also used as XTALHF1 crystal pin or EXTCLK input, with USART0 TxD, TCA0 WO0 and CCL LUT0 IN0. |
| 45 | PA1 | bidirectional | General-purpose I/O PA1 also used as XTALHF2 crystal pin, with USART0 RxD, TCA0 WO1 and CCL LUT0 IN1. |
| 46 | PA2 | bidirectional | General-purpose I/O PA2 with TWI Fm+ capability, USART0 XCK, TWI0 SDA (host/client), TCA0 WO2, TCB WO and EVOUTA. |
| 47 | PA3 | bidirectional | General-purpose I/O PA3 with TWI Fm+ capability, USART0 XDIR, TWI0 SCL (host/client), TCA0 WO3, TCB1 WO and CCL LUT0 OUT. |
| 48 | PA4 | bidirectional | General-purpose I/O PA4 with USART0 TxD (alternate), SPI0 MOSI, TCA0 WO4 and TCD0 WOA. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-48(6x6) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 49 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 1.8 | | 5.5 | V | Supply Voltage per ordering table | 633 |
| Operating temperature range (Industrial) | | -40 | | 85 | °C | I = -40°C to +85°C (Industrial) | 634 |
| CPU clock speed | | | | 24 | MHz | AVR CPU clock speeds up to 24 MHz | 1 |
| PLL input frequency | | 16 | | | MHz | Minimum input frequency of the PLL | 96 |
| PLL output frequency | | | | 48 | MHz | Maximum output frequency | 96 |
| External clock frequency on XTALHF1 | | | | 32 | MHz | External clock running at up to 32 MHz connected to XTALHF1 | 96 |
## CAD (KiCad official)
- Symbol: `AVR64DB48T-I`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm`
- 3D model: VQFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `avr64db48t-i-etched.step` / `avr64db48t-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `avr64db48t-i.step` / `avr64db48t-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/avr64db48t-i-datasheet.pdf) (665 pp, sha256 `adfeb5005d481e53`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/avr64db48t-i-datasheet.pdf)