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AVR64DA48-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleravr64da48-ifactory-2.0.0extractor-text

Verified AVR64DA48-I

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR64DA48-I · VQFN-48(6x6) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 684-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-atj41lz4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr64da48-i.kicad_sym✓ avr64da48-i.kicad_mod✓ avr64da48-i.step
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Contents

README

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AVR64DA48-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-48(6x6)

AVR64DA48-I from Microchip Tech, in a VQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA5 bidirectional General purpose I/O pin PA5 with ADC0 input X5, USART0 RxD (alternate position), SPI0 MISO and TCA0 WO5 alternate functions, with a programmable digital input buffer that can be disabled for analog use.
2 PA6 bidirectional General purpose I/O pin PA6 with ADC0 input X6, USART0 XCK (alternate position), SPI0 SCK and TCA0 WOC functions, with a programmable digital input buffer that can be disabled for analog use.
3 PA7 bidirectional General purpose I/O pin PA7 with CLKOUT, ADC0 input X7, USART0 XDIR (alternate position), SPI0 SS, TCA0 WOD and EVSYS EVOUTA alternate functions.
4 PB0 bidirectional General purpose I/O pin PB0 with ADC0 input X8, USART3 TxD (alternate), TCA0 WO0 and CCL LUT4 input functions, with a programmable digital input buffer that can be disabled for analog use.
5 PB1 bidirectional General purpose I/O pin PB1 with ADC0 input X9, USART3 RxD (alternate), TCA0 WO1 and CCL LUT4 input functions, with a programmable digital input buffer that can be disabled for analog use.
6 PB2 bidirectional General purpose I/O pin PB2 with ADC0 input X10, USART3 XCK (alternate), TWI0 SDA (alternate), TCA0 WO2 and EVSYS EVOUTB functions, with a programmable digital input buffer that can be disabled for analog use.
7 PB3 bidirectional General purpose I/O pin PB3 with ADC0 input X11, USART3 XDIR (alternate), TWI0 SCL (alternate), TCA0 WO3 and CCL LUT4 output functions, with a programmable digital input buffer that can be disabled for analog use.
8 PB4 bidirectional General purpose I/O pin PB4 with ADC0 input X12, USART3 TxD (alternate), SPI0 MOSI (alternate), TCA0 WO4 and TCB/TCA alternate functions, with a programmable digital input buffer that can be disabled for analog use.
9 PB5 bidirectional General purpose I/O pin PB5 with ADC0 input X13, USART3 RxD (alternate), SPI0 MISO (alternate), TCA0 WO5 and TCB alternate functions, with a programmable digital input buffer that can be disabled for analog use.
10 PC0 bidirectional General purpose I/O pin PC0 with USART1 TxD, SPI0 MOSI (alternate), TCA0 WO0 (alternate) and CCL LUT1 input functions, with a programmable digital input buffer that can be disabled for analog use.
11 PC1 bidirectional General purpose I/O pin PC1 with USART1 RxD, SPI0 MISO (alternate), TCA0 WO1 (alternate) and CCL LUT1 input functions, with a programmable digital input buffer that can be disabled for analog use.
12 PC2 bidirectional General purpose I/O pin PC2 with TWI0 SDA (alternate), USART1 XCK, SPI0 SCK, TCA0 WO2 (alternate) and EVSYS EVOUTC functions, with a programmable digital input buffer that can be disabled for analog use.
13 PC3 bidirectional General purpose I/O pin PC3 with TWI0 SCL (alternate), USART1 XDIR, SPI0 SS, TCA0 WO3 (alternate) and CCL LUT1 output functions, with a programmable digital input buffer that can be disabled for analog use.
14 VDD power_in Digital supply voltage; all VDD pins are internally connected and must be held at the same voltage, rated 1.8-5.5V for this device.
15 GND power_in Ground reference for the digital supply domain.
16 PC4 bidirectional General purpose I/O pin PC4 with USART1 TxD (alternate), SPI0 MOSI (alternate), TCA0 WO4 (alternate) and TCB0 alternate functions, with a programmable digital input buffer.
17 PC5 bidirectional General purpose I/O pin PC5 with USART1 RxD (alternate), SPI0 MISO (alternate), TCA0 WO5 (alternate) and TCB1 alternate functions, with a programmable digital input buffer.
18 PC6 bidirectional General purpose I/O pin PC6 with USART1 XCK (alternate), SPI0 SCK (alternate), TWI0 SDA (client), TCA0 WO2 (alternate) and CCL LUT output functions, with a programmable digital input buffer.
19 PC7 bidirectional General purpose I/O pin PC7 with USART1 XDIR (alternate), SPI0 SS (alternate), TWI0 SCL (client) and EVSYS EVOUTC (alternate) functions, with a programmable digital input buffer.
20 PD0 bidirectional General purpose I/O pin PD0 with ADC0 input AIN0 (analog, rail-to-rail), PTC Y16/X16 channel, AC0 negative input and TCA0 WO0 (alternate) functions.
21 PD1 bidirectional General purpose I/O pin PD1 with ADC0 input AIN1 (analog, rail-to-rail), PTC Y17/X17 channel, AC0 zero-cross input and TCA0 WO1 (alternate) functions.
22 PD2 bidirectional General purpose I/O pin PD2 with ADC0 input AIN2 (analog, rail-to-rail), PTC Y18/X18, AC0 positive input and EVSYS EVOUTD functions, with a programmable digital input buffer.
23 PD3 bidirectional General purpose I/O pin PD3 with ADC0 input AIN3 (analog, rail-to-rail), PTC Y19/X19, AC0 negative input and TCA0 WO3 (alternate) functions.
24 PD4 bidirectional General purpose I/O pin PD4 with ADC0 input AIN4 (analog, rail-to-rail), PTC Y20/X20, AC1 positive input and TCA0 WO4 (alternate) functions.
25 PD5 bidirectional General purpose I/O pin PD5 with ADC0 input AIN5 (analog, rail-to-rail), PTC Y21/X21, AC1 negative input and TCA0 WO5 (alternate) functions.
26 PD6 bidirectional General purpose I/O pin PD6 with ADC0 input AIN6 (analog, rail-to-rail), PTC Y22/X22, AC0 positive input and DAC0 VOUT output functions.
27 PD7 bidirectional General purpose I/O pin PD7 with ADC0 input AIN7 (analog, rail-to-rail), VREFA external voltage reference input, PTC Y23/X23, AC0 negative input and EVSYS EVOUTD (alternate) functions.
28 AVDD power_in Analog supply pin for ADC, DAC, AC and VREF; internally connected to VDD on this family with no separate power domain.
29 GND power_in Ground reference for the analog supply domain.
30 PE0 bidirectional General purpose I/O pin PE0 with ADC0 input AIN8 (analog), PTC Y24/X24, USART4 TxD, SPI0 MOSI (alternate) and TCA0 WO0 (alternate) functions.
31 PE1 bidirectional General purpose I/O pin PE1 with ADC0 input AIN9 (analog), PTC Y25/X25, USART4 RxD, SPI0 MISO (alternate) and TCA0 WO1 (alternate) functions.
32 PE2 bidirectional General purpose I/O pin PE2 with ADC0 input AIN10 (analog), PTC Y26/X26, USART4 XCK, SPI0 SCK (alternate), TCA0 WO2 (alternate) and EVSYS EVOUTE functions.
33 PE3 bidirectional General purpose I/O pin PE3 with ADC0 input AIN11 (analog), PTC Y27/X27, AC1 zero-cross input, USART4 XDIR, SPI0 SS (alternate) and TCA0 WO3 (alternate) functions.
34 PF0 passive PF0 is the XTAL32K1 crystal pin for the 32.768 kHz oscillator, also usable as ADC0 input AIN16 (positive-input-only), USART2 TxD and CCL LUT3 input.
35 PF1 passive PF1 is the XTAL32K2 crystal pin for the 32.768 kHz oscillator, also usable as ADC0 input AIN17 (positive-input-only), USART2 RxD and CCL LUT3 input.
36 PF2 bidirectional General purpose I/O pin PF2 with ADC0 input AIN18 (positive-input-only), USART2 XCK, TWI0 SDA (alternate), TCA0 WO2 (alternate) and EVSYS EVOUTF functions.
37 PF3 bidirectional General purpose I/O pin PF3 with ADC0 input AIN19 (positive-input-only), USART2 XDIR, TWI0 SCL (alternate), TCA0 WO3 (alternate) and CCL LUT3 output functions.
38 PF4 bidirectional General purpose I/O pin PF4 with ADC0 input AIN20 (positive-input-only), USART2 TxD (alternate), TCA0 WO4 (alternate) and TCB alternate functions.
39 PF5 bidirectional General purpose I/O pin PF5 with ADC0 input AIN21 (positive-input-only), USART2 RxD (alternate), TCA0 WO5 (alternate) and TCB alternate functions.
40 PF6 input Input-only pin PF6, which serves as the active-low RESET pin when RSTPINCFG enables external Reset and has an internal pull-up resistor.
41 UPDI bidirectional Dedicated Unified Program and Debug Interface pin providing asynchronous half-duplex one-wire UART programming and debug communication with no other function.
42 VDD power_in Digital supply voltage; all VDD pins are internally connected and must be held at the same voltage, rated 1.8-5.5V for this device.
43 GND power_in Ground reference for the digital supply domain.
44 PA0 bidirectional General purpose I/O pin PA0 with EXTCLK external clock input, ADC0 input X0/Y0, USART0 TxD, TCA0 WO0 and CCL LUT0 input functions.
45 PA1 bidirectional General purpose I/O pin PA1 with ADC0 input X1/Y1, USART0 RxD, TCA0 WO1 and CCL LUT0 input functions.
46 PA2 bidirectional General purpose I/O pin PA2 with ADC0 input X2/Y2, TWI0 SDA (host), USART0 XCK, TCA0 WO2, EVSYS EVOUTA and CCL LUT0 input functions.
47 PA3 bidirectional General purpose I/O pin PA3 with ADC0 input X3/Y3, TWI0 SCL (host), USART0 XDIR, TCA0 WO3 (alternate) and CCL LUT1 output functions.
48 PA4 bidirectional General purpose I/O pin PA4 with ADC0 input X4/Y4, USART0 TxD (alternate), SPI0 MOSI, TCA0 WO4 and TCB alternate functions.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-48(6x6)
Category Single Chip Microcomputer/Microcontroller
Pins 49

CAD (KiCad official)

  • Symbol: AVR64DA48-I
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48(6x6) (KiCad packages3D, STEP)
  • 3D model files: avr64da48-i-etched.step / avr64da48-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr64da48-i.step / avr64da48-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (684 pp, sha256 42c2071125f65ca1, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF