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AVR32DB48T-I
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AVR32DB48T-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)
AVR32DB48T-I from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA5 | bidirectional | PORTA pin 5 general purpose I/O on VDD power domain, with alternate USART0 RxD, SPI0 MISO and TCA0 WO5 functions per the I/O multiplexing table. |
| 2 | PA6 | bidirectional | PORTA pin 6 general purpose I/O on VDD power domain, with alternate USART0 XCK, SPI0 SCK and TCA0 WOC functions per the I/O multiplexing table. |
| 3 | PA7 | bidirectional | PORTA pin 7 general purpose I/O on VDD power domain, with alternate CLKOUT, USART0 XDIR, SPI0 SS and TCA0 WOD functions per the I/O multiplexing table. |
| 4 | PB0 | bidirectional | PORTB pin 0 general purpose I/O on the VDD power domain, with alternate USART3 TxD and TCA0 WO0 functions per the I/O multiplexing table. |
| 5 | PB1 | bidirectional | PORTB pin 1 general purpose I/O on the VDD power domain, with alternate USART3 RxD and TCA0 WO1 functions per the I/O multiplexing table. |
| 6 | PB2 | bidirectional | PORTB pin 2 general purpose I/O on the VDD power domain, with alternate TWI SDA and USART3 XCK functions per the I/O multiplexing table. |
| 7 | PB3 | bidirectional | PORTB pin 3 general purpose I/O on the VDD power domain, with alternate TWI SCL and USART3 XDIR functions per the I/O multiplexing table. |
| 8 | PB4 | bidirectional | PORTB pin 4 general purpose I/O on the VDD power domain, with alternate USART3 TxD and SPI1 MOSI functions per the I/O multiplexing table. |
| 9 | PB5 | bidirectional | PORTB pin 5 general purpose I/O on the VDD power domain, with alternate USART3 RxD and SPI1 MISO functions per the I/O multiplexing table. |
| 10 | PC0 | bidirectional | PORTC pin 0 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 TxD and SPI1 MOSI functions per the I/O multiplexing table. |
| 11 | PC1 | bidirectional | PORTC pin 1 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 RxD and SPI1 MISO functions per the I/O multiplexing table. |
| 12 | PC2 | bidirectional | PORTC pin 2 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate TWI SDA and USART1 XCK functions per the I/O multiplexing table. |
| 13 | PC3 | bidirectional | PORTC pin 3 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate TWI SCL and USART1 XDIR functions per the I/O multiplexing table. |
| 14 | VDDIO2 | power_in | Supply for the MVIO pins (port C and other subset pins), which can be at a different voltage from VDD in dual-supply mode or tied to VDD in single-supply mode. |
| 15 | GND | power_in | Ground pin; the ground pins are common to VDD, AVDD and VDDIO2. |
| 16 | PC4 | bidirectional | PORTC pin 4 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 TxD and SPI1 MOSI functions per the I/O multiplexing table. |
| 17 | PC5 | bidirectional | PORTC pin 5 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 RxD and SPI1 MISO functions per the I/O multiplexing table. |
| 18 | PC6 | bidirectional | PORTC pin 6 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 XCK and SPI1 SCK functions per the I/O multiplexing table. |
| 19 | PC7 | bidirectional | PORTC pin 7 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 XDIR and SPI1 SS functions per the I/O multiplexing table. |
| 20 | PD0 | passive | PORTD pin 0 analog input AIN0 on the AVDD domain, also usable as general purpose I/O and TCA0 WO0 alternate per the multiplexing table. |
| 21 | PD1 | passive | PORTD pin 1 analog input AIN1 with OPAMP0 non-inverting input and ZCD0 input alternate per the multiplexing table. |
| 22 | PD2 | passive | PORTD pin 2 analog input AIN2 with OPAMP0 output and AINP0 alternate functions per the multiplexing table. |
| 23 | PD3 | passive | PORTD pin 3 analog input AIN3 with OPAMP0 inverting input alternate per the multiplexing table. |
| 24 | PD4 | passive | PORTD pin 4 analog input AIN4 with OPAMP1 non-inverting input alternate per the multiplexing table. |
| 25 | PD5 | passive | PORTD pin 5 analog input AIN5 with OPAMP1 output alternate per the multiplexing table. |
| 26 | PD6 | passive | PORTD pin 6 analog input AIN6 with OPAMP output and LUT2 OUT alternate per the multiplexing table. |
| 27 | PD7 | passive | PORTD pin 7 analog input AIN7 with VREFA external reference input and OPAMP1 inverting input alternate per the multiplexing table. |
| 28 | AVDD | power_in | Analog supply pin powering the I/O lines, XOSC32K and the analog peripherals; must ramp up closely with VDD and is internally connected to VDD. |
| 29 | AGND | power_in | Analog ground pin; the datasheet gives no separate electrical limits for this pin beyond the common ground. |
| 30 | PE0 | passive | PORTE pin 0 analog input AIN8 with USART4 TxD and SPI0 MOSI alternate functions per the multiplexing table. |
| 31 | PE1 | passive | PORTE pin 1 analog input AIN9 with OPAMP2 non-inverting input and USART4 RxD alternate functions per the multiplexing table. |
| 32 | PE2 | passive | PORTE pin 2 analog input AIN10 with OPAMP2 output and USART4 XCK alternate functions per the multiplexing table. |
| 33 | PE3 | passive | PORTE pin 3 analog input AIN11 with OPAMP2 inverting input and ZCD1 input alternate per the multiplexing table. |
| 34 | PF0 (XTAL32K1) | passive | Crystal connection 1 for the external 32.768 kHz oscillator XOSC32K, also general purpose I/O PF0. |
| 35 | PF1 (XTAL32K2) | passive | Crystal connection 2 for the external 32.768 kHz oscillator XOSC32K, also general purpose I/O PF1. |
| 36 | PF2 | bidirectional | PORTF pin 2 analog input AIN18 with TWI SDA and USART2 XCK alternate functions per the multiplexing table. |
| 37 | PF3 | bidirectional | PORTF pin 3 analog input AIN19 with TWI SCL and USART2 XDIR alternate functions per the multiplexing table. |
| 38 | PF4 | bidirectional | PORTF pin 4 analog input AIN20 with USART2 TxD alternate function per the multiplexing table. |
| 39 | PF5 | bidirectional | PORTF pin 5 analog input AIN21 with USART2 RxD alternate function per the multiplexing table. |
| 40 | PF6 (RESET) | input | Input-only pin; configured as external RESET with pull-up when the RSTPINCFG fuse selects RESET, with a noise filter on short low pulses. |
| 41 | UPDI | input | Unified Program and Debug Interface pin, a dedicated one-wire UART pin for programming and debugging with no other function. |
| 42 | VDD | power_in | Supply pin powering the I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD and AVDD pins. |
| 43 | GND | power_in | Ground pin; the ground pins are common to VDD, AVDD and VDDIO2. |
| 44 | PA0 (XTALHF1) | passive | Crystal connection 1 for the high-frequency oscillator XOSCHF, also general purpose I/O PA0 and EXTCLK alternate. |
| 45 | PA1 (XTALHF2) | passive | Crystal connection 2 for the high-frequency oscillator XOSCHF, also general purpose I/O PA1 and USART0 RxD alternate. |
| 46 | PA2 | bidirectional | PORTA pin 2 general purpose I/O on the VDD domain, with alternate TWI SDA, USART0 XCK and TCA0 WO2 functions per the multiplexing table. |
| 47 | PA3 | bidirectional | PORTA pin 3 general purpose I/O on the VDD domain, with alternate TWI SCL, USART0 XDIR and TCA0 WO3 functions per the multiplexing table. |
| 48 | PA4 | bidirectional | PORTA pin 4 general purpose I/O on the VDD domain, with alternate USART0 TxD, SPI0 MOSI and TCA0 WO4 functions per the multiplexing table. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-48(7x7) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
AVR32DB48T-I - Footprint:
Package_QFP:TQFP-48_7x7mm_P0.5mm - 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
avr32db48t-i-etched.step/avr32db48t-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);avr32db48t-i.step/avr32db48t-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (665 pp, sha256
adfeb5005d481e53, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AVR32DB48T-I
**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)
AVR32DB48T-I from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA5 | bidirectional | PORTA pin 5 general purpose I/O on VDD power domain, with alternate USART0 RxD, SPI0 MISO and TCA0 WO5 functions per the I/O multiplexing table. |
| 2 | PA6 | bidirectional | PORTA pin 6 general purpose I/O on VDD power domain, with alternate USART0 XCK, SPI0 SCK and TCA0 WOC functions per the I/O multiplexing table. |
| 3 | PA7 | bidirectional | PORTA pin 7 general purpose I/O on VDD power domain, with alternate CLKOUT, USART0 XDIR, SPI0 SS and TCA0 WOD functions per the I/O multiplexing table. |
| 4 | PB0 | bidirectional | PORTB pin 0 general purpose I/O on the VDD power domain, with alternate USART3 TxD and TCA0 WO0 functions per the I/O multiplexing table. |
| 5 | PB1 | bidirectional | PORTB pin 1 general purpose I/O on the VDD power domain, with alternate USART3 RxD and TCA0 WO1 functions per the I/O multiplexing table. |
| 6 | PB2 | bidirectional | PORTB pin 2 general purpose I/O on the VDD power domain, with alternate TWI SDA and USART3 XCK functions per the I/O multiplexing table. |
| 7 | PB3 | bidirectional | PORTB pin 3 general purpose I/O on the VDD power domain, with alternate TWI SCL and USART3 XDIR functions per the I/O multiplexing table. |
| 8 | PB4 | bidirectional | PORTB pin 4 general purpose I/O on the VDD power domain, with alternate USART3 TxD and SPI1 MOSI functions per the I/O multiplexing table. |
| 9 | PB5 | bidirectional | PORTB pin 5 general purpose I/O on the VDD power domain, with alternate USART3 RxD and SPI1 MISO functions per the I/O multiplexing table. |
| 10 | PC0 | bidirectional | PORTC pin 0 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 TxD and SPI1 MOSI functions per the I/O multiplexing table. |
| 11 | PC1 | bidirectional | PORTC pin 1 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 RxD and SPI1 MISO functions per the I/O multiplexing table. |
| 12 | PC2 | bidirectional | PORTC pin 2 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate TWI SDA and USART1 XCK functions per the I/O multiplexing table. |
| 13 | PC3 | bidirectional | PORTC pin 3 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate TWI SCL and USART1 XDIR functions per the I/O multiplexing table. |
| 14 | VDDIO2 | power_in | Supply for the MVIO pins (port C and other subset pins), which can be at a different voltage from VDD in dual-supply mode or tied to VDD in single-supply mode. |
| 15 | GND | power_in | Ground pin; the ground pins are common to VDD, AVDD and VDDIO2. |
| 16 | PC4 | bidirectional | PORTC pin 4 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 TxD and SPI1 MOSI functions per the I/O multiplexing table. |
| 17 | PC5 | bidirectional | PORTC pin 5 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 RxD and SPI1 MISO functions per the I/O multiplexing table. |
| 18 | PC6 | bidirectional | PORTC pin 6 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 XCK and SPI1 SCK functions per the I/O multiplexing table. |
| 19 | PC7 | bidirectional | PORTC pin 7 general purpose I/O on the MVIO domain powered by VDDIO2, with alternate USART1 XDIR and SPI1 SS functions per the I/O multiplexing table. |
| 20 | PD0 | passive | PORTD pin 0 analog input AIN0 on the AVDD domain, also usable as general purpose I/O and TCA0 WO0 alternate per the multiplexing table. |
| 21 | PD1 | passive | PORTD pin 1 analog input AIN1 with OPAMP0 non-inverting input and ZCD0 input alternate per the multiplexing table. |
| 22 | PD2 | passive | PORTD pin 2 analog input AIN2 with OPAMP0 output and AINP0 alternate functions per the multiplexing table. |
| 23 | PD3 | passive | PORTD pin 3 analog input AIN3 with OPAMP0 inverting input alternate per the multiplexing table. |
| 24 | PD4 | passive | PORTD pin 4 analog input AIN4 with OPAMP1 non-inverting input alternate per the multiplexing table. |
| 25 | PD5 | passive | PORTD pin 5 analog input AIN5 with OPAMP1 output alternate per the multiplexing table. |
| 26 | PD6 | passive | PORTD pin 6 analog input AIN6 with OPAMP output and LUT2 OUT alternate per the multiplexing table. |
| 27 | PD7 | passive | PORTD pin 7 analog input AIN7 with VREFA external reference input and OPAMP1 inverting input alternate per the multiplexing table. |
| 28 | AVDD | power_in | Analog supply pin powering the I/O lines, XOSC32K and the analog peripherals; must ramp up closely with VDD and is internally connected to VDD. |
| 29 | AGND | power_in | Analog ground pin; the datasheet gives no separate electrical limits for this pin beyond the common ground. |
| 30 | PE0 | passive | PORTE pin 0 analog input AIN8 with USART4 TxD and SPI0 MOSI alternate functions per the multiplexing table. |
| 31 | PE1 | passive | PORTE pin 1 analog input AIN9 with OPAMP2 non-inverting input and USART4 RxD alternate functions per the multiplexing table. |
| 32 | PE2 | passive | PORTE pin 2 analog input AIN10 with OPAMP2 output and USART4 XCK alternate functions per the multiplexing table. |
| 33 | PE3 | passive | PORTE pin 3 analog input AIN11 with OPAMP2 inverting input and ZCD1 input alternate per the multiplexing table. |
| 34 | PF0 (XTAL32K1) | passive | Crystal connection 1 for the external 32.768 kHz oscillator XOSC32K, also general purpose I/O PF0. |
| 35 | PF1 (XTAL32K2) | passive | Crystal connection 2 for the external 32.768 kHz oscillator XOSC32K, also general purpose I/O PF1. |
| 36 | PF2 | bidirectional | PORTF pin 2 analog input AIN18 with TWI SDA and USART2 XCK alternate functions per the multiplexing table. |
| 37 | PF3 | bidirectional | PORTF pin 3 analog input AIN19 with TWI SCL and USART2 XDIR alternate functions per the multiplexing table. |
| 38 | PF4 | bidirectional | PORTF pin 4 analog input AIN20 with USART2 TxD alternate function per the multiplexing table. |
| 39 | PF5 | bidirectional | PORTF pin 5 analog input AIN21 with USART2 RxD alternate function per the multiplexing table. |
| 40 | PF6 (RESET) | input | Input-only pin; configured as external RESET with pull-up when the RSTPINCFG fuse selects RESET, with a noise filter on short low pulses. |
| 41 | UPDI | input | Unified Program and Debug Interface pin, a dedicated one-wire UART pin for programming and debugging with no other function. |
| 42 | VDD | power_in | Supply pin powering the I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD and AVDD pins. |
| 43 | GND | power_in | Ground pin; the ground pins are common to VDD, AVDD and VDDIO2. |
| 44 | PA0 (XTALHF1) | passive | Crystal connection 1 for the high-frequency oscillator XOSCHF, also general purpose I/O PA0 and EXTCLK alternate. |
| 45 | PA1 (XTALHF2) | passive | Crystal connection 2 for the high-frequency oscillator XOSCHF, also general purpose I/O PA1 and USART0 RxD alternate. |
| 46 | PA2 | bidirectional | PORTA pin 2 general purpose I/O on the VDD domain, with alternate TWI SDA, USART0 XCK and TCA0 WO2 functions per the multiplexing table. |
| 47 | PA3 | bidirectional | PORTA pin 3 general purpose I/O on the VDD domain, with alternate TWI SCL, USART0 XDIR and TCA0 WO3 functions per the multiplexing table. |
| 48 | PA4 | bidirectional | PORTA pin 4 general purpose I/O on the VDD domain, with alternate USART0 TxD, SPI0 MOSI and TCA0 WO4 functions per the multiplexing table. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-48(7x7) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 48 |
## CAD (KiCad official)
- Symbol: `AVR32DB48T-I`
- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`
- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `avr32db48t-i-etched.step` / `avr32db48t-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `avr32db48t-i.step` / `avr32db48t-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/avr32db48t-i-datasheet.pdf) (665 pp, sha256 `adfeb5005d481e53`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/avr32db48t-i-datasheet.pdf)