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AVR32DB48-E

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleravr32db48-efactory-2.0.0extractor-text

Verified AVR32DB48-E

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR32DB48-E · VQFN-48(6x6) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 665-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-miuikzyz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr32db48-e.kicad_sym✓ avr32db48-e.kicad_mod✓ avr32db48-e.step
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Ray Publish 0.1.0 554400f 2d ago

AVR32DB48-E

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-48(6x6)

AVR32DB48-E from Microchip Tech, in a VQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA5 bidirectional General-purpose I/O pin PA5 on the VDD domain, with alternate functions USART0 RxD, SPI0 MISO, TCA0 WO5 and TCD0 WOB.
2 PA6 bidirectional General-purpose I/O pin PA6 on the VDD domain, with alternate functions USART0 XCK, SPI0 SCK, TCD0 WOC and CCL LUT0-OUT.
3 PA7 bidirectional General-purpose I/O pin PA7 on the VDD domain, with functions CLKOUT, ZCD0-2 OUT, USART0 XDIR, SPI0 SS, TCD0 WOD and EVOUTA.
4 PB0 bidirectional General-purpose I/O pin PB0 on the VDD domain, with functions USART3 TxD, TCA0/TCA1 WO0 and CCL LUT4-IN0.
5 PB1 bidirectional General-purpose I/O pin PB1 on the VDD domain, with functions USART3 RxD, TCA0/TCA1 WO1 and CCL LUT4-IN1.
6 PB2 bidirectional General-purpose I/O pin PB2 on the VDD domain, with functions USART3 XCK, TWI1 SDA (host or client), TCA0/TCA1 WO2, EVOUTB and CCL LUT4-IN2.
7 PB3 bidirectional General-purpose I/O pin PB3 on the VDD domain, with functions USART3 XDIR, TWI1 SCL (host or client), TCA0/TCA1 WO3 and CCL LUT4-OUT.
8 PB4 bidirectional General-purpose I/O pin PB4 on the VDD domain, with functions USART3 TxD, SPI1 MOSI, TCA0/TCA1 WO4, TCB2 WO and TCD0 WOA.
9 PB5 bidirectional General-purpose I/O pin PB5 on the VDD domain, with functions USART3 RxD, SPI1 MISO, TCA0/TCA1 WO5, TCB3 WO and TCD0 WOB.
10 PC0 bidirectional General-purpose I/O pin PC0 on the VDDIO2 (MVIO) domain, with functions USART1 TxD, SPI1 MOSI, TCA0 WO0, TCB2 WO and CCL LUT1-IN0.
11 PC1 bidirectional General-purpose I/O pin PC1 on the VDDIO2 (MVIO) domain, with functions USART1 RxD, SPI1 MISO, TCA0 WO1, TCB3 WO and CCL LUT1-IN1.
12 PC2 bidirectional General-purpose I/O pin PC2 on the VDDIO2 (MVIO) domain, with TWI Fm+ capability and functions USART1 XCK, SPI1 SCK, TWI0 SDA, TCA0 WO2, EVOUTC and CCL LUT1-IN2.
13 PC3 bidirectional General-purpose I/O pin PC3 on the VDDIO2 (MVIO) domain, with TWI Fm+ capability and functions USART1 XDIR, SPI1 SS, TWI0 SCL, TCA0 WO3 and CCL LUT1-OUT.
14 VDDIO2 power_in Supply pin for the VDDIO2 power domain that powers the MVIO I/O lines (port C), which can be at a different voltage from VDD in dual-supply mode and must be tied to VDD in single-supply mode.
15 GND power_in Ground pin, common to the VDD, AVDD and VDDIO2 domains.
16 PC4 bidirectional General-purpose I/O pin PC4 on the VDDIO2 (MVIO) domain, with alternate functions USART1 TxD, SPI1 MOSI, TCA0 WO4 and TCB0 WO.
17 PC5 bidirectional General-purpose I/O pin PC5 on the VDDIO2 (MVIO) domain, with alternate functions USART1 RxD, SPI1 MISO, TCA0 WO5 and TCB1 WO.
18 PC6 bidirectional General-purpose I/O pin PC6 on the VDDIO2 (MVIO) domain, with alternate functions ZCD0-2 OUT, USART1 XCK, SPI1 SCK, TWI0 SDA (client only), TCB2 WO and CCL LUT1-OUT.
19 PC7 bidirectional General-purpose I/O pin PC7 on the VDDIO2 (MVIO) domain, with alternate functions ZCD0-2 OUT, USART1 XDIR, SPI1 SS, TWI0 SCL (client only) and EVOUTC.
20 PD0 bidirectional General-purpose I/O pin PD0 on the AVDD domain, with analog input ADC0 AIN0, AC0-2 AINN1 and alternate function TCA0 WO0.
21 PD1 bidirectional General-purpose I/O pin PD1 on the AVDD domain, with analog input ADC0 AIN1, OPAMP OP0 INP, ZCD0 ZCIN and alternate function TCA0 WO1.
22 PD2 bidirectional General-purpose I/O pin PD2 on the AVDD domain, with analog input ADC0 AIN2, AC0-2 AINP0, OPAMP OP0 OUT, EVOUTD and CCL LUT2-IN2.
23 PD3 bidirectional General-purpose I/O pin PD3 on the AVDD domain, with analog input ADC0 AIN3, AC AINN0/AINP1, OPAMP OP0 INN and CCL LUT2-OUT.
24 PD4 bidirectional General-purpose I/O pin PD4 on the AVDD domain, with analog input ADC0 AIN4, AC1/AC2 AINP2/AINP1, OPAMP OP1 INP and alternate function TCA0 WO4.
25 PD5 bidirectional General-purpose I/O pin PD5 on the AVDD domain, with analog input ADC0 AIN5, AC1 AINN0, OPAMP OP1 OUT and alternate function TCA0 WO5.
26 PD6 bidirectional General-purpose I/O pin PD6 on the AVDD domain, with analog input ADC0 AIN6, AC0-2 AINP3, DAC0 OUT and CCL LUT2-OUT.
27 PD7 bidirectional General-purpose I/O pin PD7 on the AVDD domain, with external voltage reference input VREFA, analog input ADC0 AIN7, AC AINN2/AINN0, OPAMP OP1 INN and EVOUTD.
28 AVDD power_in Supply pin for the analog power domain (I/O lines, XOSC32K and analog peripherals), internally connected to VDD, and the same voltage must be applied to all VDD and AVDD pins.
29 GND power_in Analog ground pin (AGND), common to the VDD, AVDD and VDDIO2 domains.
30 PE0 bidirectional General-purpose I/O pin PE0 on the AVDD domain, with analog input ADC0 AIN8, AC0 AINP1, USART4 TxD and alternate functions SPI0 MOSI and TCA0 WO0.
31 PE1 bidirectional General-purpose I/O pin PE1 on the AVDD domain, with analog input ADC0 AIN9, AC2 AINP2, OPAMP OP2 INP and USART4 RxD.
32 PE2 bidirectional General-purpose I/O pin PE2 on the AVDD domain, with analog input ADC0 AIN10, AC0 AINP2, OPAMP OP2 OUT, USART4 XCK and EVOUTE.
33 PE3 bidirectional General-purpose I/O pin PE3 on the AVDD domain, with analog input ADC0 AIN11, OPAMP OP2 INN, ZCD1 ZCIN and USART4 XDIR.
34 PF0 bidirectional General-purpose I/O pin PF0 on the AVDD domain, with external 32.768 kHz crystal pin XTAL32K1, ADC0 AIN16 (not usable as a negative differential input), USART2 TxD and CCL LUT3-IN0.
35 PF1 bidirectional General-purpose I/O pin PF1 on the AVDD domain, with external 32.768 kHz crystal pin XTAL32K2, ADC0 AIN17 (not usable as a negative differential input), USART2 RxD and CCL LUT3-IN1.
36 PF2 bidirectional General-purpose I/O pin PF2 on the AVDD domain, with TWI Fm+ capability, ADC0 AIN18 (not usable as a negative differential input), USART2 XCK, TWI1 SDA, EVOUTF and CCL LUT3-IN2.
37 PF3 bidirectional General-purpose I/O pin PF3 on the AVDD domain, with TWI Fm+ capability, ADC0 AIN19 (not usable as a negative differential input), USART2 XDIR, TWI1 SCL and CCL LUT3-OUT.
38 PF4 bidirectional General-purpose I/O pin PF4 on the AVDD domain, with ADC0 AIN20 (not usable as a negative differential input) and alternate functions USART2 TxD, TCA0 WO4 and TCB0 WO.
39 PF5 bidirectional General-purpose I/O pin PF5 on the AVDD domain, with ADC0 AIN21 (not usable as a negative differential input) and alternate functions USART2 RxD, TCA0 WO5 and TCB1 WO.
40 PF6 (RESET) input Input-only pin PF6 that serves as the external RESET input when enabled by the RSTPINCFG fuse, holding the device in reset while low.
41 UPDI bidirectional Dedicated Unified Program and Debug Interface pin for one-wire, half-duplex asynchronous UART programming and debugging, with no other function.
42 VDD power_in Supply pin that powers I/O lines, XOSCHF and the internal voltage regulator.
43 GND power_in Ground pin, common to the VDD, AVDD and VDDIO2 domains.
44 PA0 bidirectional General-purpose I/O pin PA0 on the VDD domain, with high-frequency crystal pin XTALHF1, EXTCLK input, USART0 TxD, TCA0 WO0 and CCL LUT0-IN0.
45 PA1 bidirectional General-purpose I/O pin PA1 on the VDD domain, with high-frequency crystal pin XTALHF2, USART0 RxD, TCA0 WO1 and CCL LUT0-IN1.
46 PA2 bidirectional General-purpose I/O pin PA2 on the VDD domain, with TWI Fm+ capability and functions USART0 XCK, TWI0 SDA (host or client), TCA0 WO2, TCB0 WO, EVOUTA and CCL LUT0-IN2.
47 PA3 bidirectional General-purpose I/O pin PA3 on the VDD domain, with TWI Fm+ capability and functions USART0 XDIR, TWI0 SCL (host or client), TCA0 WO3, TCB1 WO and CCL LUT0-OUT.
48 PA4 bidirectional General-purpose I/O pin PA4 on the VDD domain, with alternate functions USART0 TxD, SPI0 MOSI, TCA0 WO4 and TCD0 WOA.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-48(6x6)
Category Single Chip Microcomputer/Microcontroller
Pins 49

CAD (KiCad official)

  • Symbol: AVR32DB48-E
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48(6x6) (KiCad packages3D, STEP)
  • 3D model files: avr32db48-e-etched.step / avr32db48-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr32db48-e.step / avr32db48-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (665 pp, sha256 adfeb5005d481e53, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF