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AVR128DB64T-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleravr128db64t-ifactory-2.0.0extractor-text

Verified AVR128DB64T-I

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR128DB64T-I · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 660-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-70bsyypt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr128db64t-i.kicad_sym✓ avr128db64t-i.kicad_mod✓ avr128db64t-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers avr128db64t-i: viewers · Ray 5d ago
avr128db64t-i-etched.glb Publish 0.1.0 · Ray 5d ago
avr128db64t-i-etched.step avr128db64t-i: factory component page (tier=mfr) · Ray 5d ago
avr128db64t-i-hero.glb avr128db64t-i: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
avr128db64t-i-hero.overlay.json Publish 0.1.0 · Ray 5d ago
avr128db64t-i.glb Publish 0.1.0 · Ray 5d ago
avr128db64t-i.kicad_mod Publish 0.1.0 · Ray 5d ago
avr128db64t-i.kicad_sym Publish 0.1.0 · Ray 5d ago
avr128db64t-i.lbr Publish 0.1.0 · Ray 5d ago
avr128db64t-i.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 64 pins · Ray 5d ago

AVR128DB64T-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

AVR128DB64T-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose I/O pin PA3, with USART0 XDIR, TWI0 SCL master and TCA0 WO3 alternate functions and LUT0 OUT.
2 PA4 bidirectional General-purpose I/O pin PA4, with USART0 TxD alternate function, SPI0 MOSI, TCA0 WO4 and EVSYS WOA.
3 PA5 bidirectional General-purpose I/O pin PA5, with USART0 RxD alternate function, SPI0 MISO, TCA0 WO5 and EVSYS WOB.
4 PA6 bidirectional General-purpose I/O pin PA6, with USART0 XCK alternate function, SPI0 SCK, WOC and LUT0 OUT.
5 PA7 bidirectional General-purpose I/O pin PA7, with CLKOUT, USART0 XDIR alternate function, SPI0 SS, WOD and EVSYS OUT.
6 VDD power_in Power supply pin for the device (VDD).
7 GND power_in Ground pin.
8 PB0 bidirectional General-purpose I/O pin PB0, with USART3 TxD, TCA0 WO0 alternate and LUT4 IN0.
9 PB1 bidirectional General-purpose I/O pin PB1, with USART3 RxD, TCA0 WO1 alternate and LUT4 IN1.
10 PB2 bidirectional General-purpose I/O pin PB2, with USART3 XCK, TWI0 SDA master alternate, TCA0 WO2 alternate and EVSYS OUTB.
11 PB3 bidirectional General-purpose I/O pin PB3, with USART3 XDIR, TWI0 SCL master alternate, TCA0 WO3 alternate and LUT4 OUT.
12 PB4 bidirectional General-purpose I/O pin PB4, with USART3 TxD alternate, SPI0 MOSI alternate, TCA0 WO4 alternate and WOA alternate.
13 PB5 bidirectional General-purpose I/O pin PB5, with USART3 RxD alternate, SPI0 MISO alternate, TCA0 WO5 alternate and WOB alternate.
14 PB6 bidirectional General-purpose I/O pin PB6, with USART3 XCK alternate, SPI0 SCK alternate, TWI0 SDA slave alternate, WOC alternate and LUT4 OUT alternate.
15 PB7 bidirectional General-purpose I/O pin PB7, with USART3 XDIR alternate, SPI0 SS alternate, TWI0 SCL slave alternate, WOD alternate and EVSYS OUTB alternate.
16 PC0 bidirectional General-purpose I/O pin PC0, with USART1 TxD, SPI0 MOSI alternate, TCA0 WO0 alternate, TCB0 WO and LUT1 IN0.
17 PC1 bidirectional General-purpose I/O pin PC1, with USART1 RxD, SPI0 MISO alternate, TCA0 WO1 alternate, TCB1 WO alternate and LUT1 IN1.
18 PC2 bidirectional General-purpose I/O pin PC2, with TWI0 Fm+ capability, USART1 XCK, SPI0 SCK, TWI0 SDA master alternate, TCA0 WO2 alternate, EVSYS OUTC and LUT1 IN2.
19 PC3 bidirectional General-purpose I/O pin PC3, with TWI0 Fm+ capability, USART1 XDIR, SPI0 SS, TWI0 SCL master alternate, TCA0 WO3 alternate and LUT1 OUT.
20 VDDIO2 power_in Power supply pin for the MVIO domain (VDDIO2), supplying the multi-voltage I/O pins.
21 GND power_in Ground pin.
22 PC4 bidirectional General-purpose I/O pin PC4, with USART1 TxD alternate, SPI0 MOSI alternate, TCA0 WO4 alternate and TCA0 WO0 alternate.
23 PC5 bidirectional General-purpose I/O pin PC5, with USART1 RxD alternate, SPI0 MISO alternate, TCA0 WO5 alternate and TCA0 WO1 alternate.
24 PC6 bidirectional General-purpose I/O pin PC6, with USART1 XCK alternate, SPI0 SCK alternate, TWI0 SDA slave alternate, TCA0 WO2 alternate and LUT1 OUT alternate.
25 PC7 bidirectional General-purpose I/O pin PC7, with USART1 XDIR alternate, SPI0 SS alternate, TWI0 SCL slave alternate and EVSYS OUTC alternate.
26 PD0 bidirectional General-purpose I/O pin PD0, with analog input AIN0, ADC negative input AINN1 alternates, TCA0 WO0 alternate and LUT2 IN0.
27 PD1 bidirectional General-purpose I/O pin PD1, with analog input AIN1, OPAMP0 INP, ZCD0 ZCIN, TCA0 WO1 alternate and LUT2 IN1.
28 PD2 bidirectional General-purpose I/O pin PD2, with analog input AIN2, ADC positive input AINP0 alternates, OPAMP0 OUT, TCA0 WO2 alternate, EVSYS OUTD and LUT2 IN2.
29 PD3 bidirectional General-purpose I/O pin PD3, with analog input AIN3, ADC negative input AINN0, OPAMP0 INN, TCA0 WO3 alternate and LUT2 OUT.
30 PD4 bidirectional General-purpose I/O pin PD4, with analog input AIN4, ADC positive input AINP2 alternate, OPAMP1 INP and TCA0 WO4 alternate.
31 PD5 bidirectional General-purpose I/O pin PD5, with analog input AIN5, ADC negative input AINN0 alternate, OPAMP1 OUT and TCA0 WO5 alternate.
32 PD6 bidirectional General-purpose I/O pin PD6, with analog input AIN6, ADC positive input AINP3 alternates, OUT of the ZCD and LUT2 OUT alternate.
33 PD7 bidirectional General-purpose I/O pin PD7, with VREFA external voltage reference input, analog input AIN7, OPAMP1 INN and EVSYS OUTD alternate.
34 AVDD power_in Analog supply pin (AVDD), internally connected to VDD on this device family.
35 AGND power_in Analog ground pin.
36 PE0 bidirectional General-purpose I/O pin PE0, with analog input AIN8, ADC positive input AINP1, USART4 TxD, SPI0 MOSI alternate and TCA0 WO0 alternate.
37 PE1 bidirectional General-purpose I/O pin PE1, with analog input AIN9, ADC positive input AINP2 alternate, OPAMP2 INP, USART4 RxD, SPI0 MISO alternate and TCA0 WO1 alternate.
38 PE2 bidirectional General-purpose I/O pin PE2, with analog input AIN10, ADC positive input AINP2, OPAMP2 OUT, USART4 XCK, SPI0 SCK alternate, TCA0 WO2 alternate and EVSYS OUTE.
39 PE3 bidirectional General-purpose I/O pin PE3, with analog input AIN11, OPAMP2 INN, ZCD1 ZCIN, USART4 XDIR, SPI0 SS alternate and TCA0 WO3 alternate.
40 PE4 bidirectional General-purpose I/O pin PE4, with analog input AIN12, USART4 TxD alternate and TCA0 WO4 alternate.
41 PE5 bidirectional General-purpose I/O pin PE5, with analog input AIN13, USART4 RxD alternate and TCA0 WO5 alternate.
42 PE6 bidirectional General-purpose I/O pin PE6, with analog input AIN14, USART4 XCK alternate and TCA0 WO2 alternate.
43 PE7 bidirectional General-purpose I/O pin PE7, with analog input AIN15, ZCD2 ZCIN, USART4 XDIR alternate and EVSYS OUTE alternate.
44 PF0 bidirectional General-purpose I/O pin PF0, also the XTAL32K1 32.768 kHz crystal connection, with analog input AIN16, USART2 TxD, TCA0 WO0 alternate, WOA alternate and LUT3 IN0.
45 PF1 bidirectional General-purpose I/O pin PF1, also the XTAL32K2 32.768 kHz crystal connection, with analog input AIN17, USART2 RxD, TCA0 WO1 alternate, WOB alternate and LUT3 IN1.
46 PF2 bidirectional General-purpose I/O pin PF2, with analog input AIN18, TWI0 Fm+ capability, USART2 XCK, TWI0 SDA master alternate, TCA0 WO2 alternate, WOC alternate, EVSYS OUTF and LUT3 IN2.
47 PF3 bidirectional General-purpose I/O pin PF3, with analog input AIN19, TWI0 Fm+ capability, USART2 XDIR, TWI0 SCL master alternate, TCA0 WO3 alternate, WOD alternate and LUT3 OUT.
48 PF4 bidirectional General-purpose I/O pin PF4, with analog input AIN20, USART2 TxD alternate, TCA0 WO4 alternate and TCA0 WO alternate.
49 PF5 bidirectional General-purpose I/O pin PF5, with analog input AIN21, USART2 RxD alternate, TCA0 WO5 alternate and TCA0 WO alternate.
50 PF6 input Input-only pin PF6, which serves as the RESET pin when external reset is enabled and has a pull-up in that configuration.
51 UPDI input Unified Program and Debug Interface pin, a digital input for programming and debugging.
52 PG0 bidirectional General-purpose I/O pin PG0, with USART5 TxD, TCA0 WO0 alternate and LUT5 IN0.
53 PG1 bidirectional General-purpose I/O pin PG1, with USART5 RxD, TCA0 WO1 alternate and LUT5 IN1.
54 PG2 bidirectional General-purpose I/O pin PG2, with USART5 XCK, TCA0 WO2 alternate, EVSYS OUTG and LUT5 IN2.
55 PG3 bidirectional General-purpose I/O pin PG3, with USART5 XDIR, TCA0 WO3 alternate and LUT5 OUT.
56 VDD power_in Power supply pin for the device (VDD).
57 GND power_in Ground pin.
58 PG4 bidirectional General-purpose I/O pin PG4, with USART5 TxD alternate, SPI0 MOSI alternate, TCA0 WO4 alternate and WOA alternate.
59 PG5 bidirectional General-purpose I/O pin PG5, with USART5 RxD alternate, SPI0 MISO alternate, TCA0 WO5 alternate and WOB alternate.
60 PG6 bidirectional General-purpose I/O pin PG6, with USART5 XCK alternate, SPI0 SCK alternate, WOC alternate and LUT5 OUT alternate.
61 PG7 bidirectional General-purpose I/O pin PG7, with USART5 XDIR alternate, SPI0 SS alternate, WOD alternate and EVSYS OUTG alternate.
62 PA0 bidirectional General-purpose I/O pin PA0, also the XTALHF1 high-frequency crystal connection and EXTCLK, with USART0 TxD, TCA0 WO0 and LUT0 IN0 alternates.
63 PA1 bidirectional General-purpose I/O pin PA1, also the XTALHF2 high-frequency crystal connection, with USART0 RxD, TCA0 WO1 and LUT0 IN1 alternates.
64 PA2 bidirectional General-purpose I/O pin PA2, with TWI0 Fm+ capability, USART0 XCK, TWI0 SDA master alternate, TCA0 WO2 alternate, EVSYS OUTA and LUT0 IN2.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage 1.8 5.5 V Supply Voltage column, ordering table row AVR128DB64T-I/PT (TQFP, Tape & Reel) 629
Temperature Range -40 85 °C Temperature Range column, ordering table row AVR128DB64T-I/PT (TQFP, Tape & Reel) 629

CAD (KiCad official)

  • Symbol: AVR128DB64T-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: avr128db64t-i-etched.step / avr128db64t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr128db64t-i.step / avr128db64t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (660 pp, sha256 1fb225fb44c6b2af, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF