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AVR128DB64-I/PT

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Microchip Tech Pre-ordered MCUs, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersavr128db64-ifactory-2.0.0extractor-text

Verified AVR128DB64-I/PT

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR128DB64-I/PT · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 660-page datasheet
  • ✓distributor: lcsc C1019769, digikey 150-AVR128DB64-I/PT-ND, mouser 579-AVR128DB64-I/PT
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zysc_6gg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.654)
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 74 kB, viewers/symbol.html 41 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr128db64-i-pt.kicad_sym✓ avr128db64-i-pt.kicad_mod✓ avr128db64-i-pt.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers avr128db64-i-pt: viewers rendered from the public page · Ray
avr128db64-i-pt-etched.glb avr128db64-i-pt: factory component page (tier=mfr) · Ray
avr128db64-i-pt-etched.step avr128db64-i-pt: factory component page (tier=mfr) · Ray
avr128db64-i-pt-hero.glb avr128db64-i-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
avr128db64-i-pt-hero.overlay.json avr128db64-i-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
avr128db64-i-pt.glb Publish 0.1.0 · Ray
avr128db64-i-pt.kicad_mod Publish 0.1.0 · Ray
avr128db64-i-pt.kicad_sym Publish 0.1.0 · Ray
avr128db64-i-pt.lbr Publish 0.1.0 · Ray
avr128db64-i-pt.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 64 pins · Ray

AVR128DB64-I

Microchip Tech · Pre-ordered MCUs · TQFP-64(10x10)

AVR128DB64-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose bidirectional I/O pin PA3 on PORTA with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include TWI (Fm+ capable), USART0 XDIR, TCA0 WO3 and LUT0 OUT.
2 PA4 bidirectional General-purpose bidirectional I/O pin PA4 on PORTA with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART0 TxD, SPI0 MOSI, TCA0 WO4 and WOA.
3 PA5 bidirectional General-purpose bidirectional I/O pin PA5 on PORTA with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART0 RxD, SPI0 MISO, TCA0 WO5 and WOB.
4 PA6 bidirectional General-purpose bidirectional I/O pin PA6 on PORTA with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART0 XCK, SPI0 SCK, TCA0 WOC and LUT0 OUT.
5 PA7 bidirectional General-purpose bidirectional I/O pin PA7 on PORTA with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include CLKOUT, SPI0 SS, TCA0 WOD and EVOUTA.
6 VDD power_in Digital supply pin of the device; each VDD/GND pair needs its own decoupling capacitor placed close to the pins.
7 GND power_in Ground reference pin of the device; each supply pin pair needs its own decoupling capacitor.
8 PB0 bidirectional General-purpose bidirectional I/O pin PB0 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART3 TxD, TCA0 WO0 and LUT4 IN0.
9 PB1 bidirectional General-purpose bidirectional I/O pin PB1 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART3 RxD, TCA0 WO1 and LUT4 IN1.
10 PB2 bidirectional General-purpose bidirectional I/O pin PB2 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include TWI, USART3 XCK, TWI SDA (master/slave), TCA0 WO2 and EVSYS EVOUTB.
11 PB3 bidirectional General-purpose bidirectional I/O pin PB3 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include TWI, USART3 XDIR, TWI SCL (master/slave), TCA0 WO3 and LUT4 OUT.
12 PB4 bidirectional General-purpose bidirectional I/O pin PB4 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART3 TxD, SPI1 MOSI, TCA0 WO4 and TCB0 WOA.
13 PB5 bidirectional General-purpose bidirectional I/O pin PB5 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART3 RxD, SPI1 MISO, TCA0 WO5 and TCB0 WOB.
14 PB6 bidirectional General-purpose bidirectional I/O pin PB6 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART3 XCK, SPI1 SCK, TWI SDA (slave), TCA0 WOC and LUT4 OUT.
15 PB7 bidirectional General-purpose bidirectional I/O pin PB7 on PORTB with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART3 XDIR, SPI1 SS, TWI SCL (slave), TCA0 WOD and EVSYS EVOUTB.
16 PC0 bidirectional Multi-voltage I/O pin PC0 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART1 TxD, SPI0 MOSI, TCA0 WO0 and LUT1 IN0.
17 PC1 bidirectional Multi-voltage I/O pin PC1 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART1 RxD, SPI0 MISO, TCA0 WO1 and LUT1 IN1.
18 PC2 bidirectional Multi-voltage I/O pin PC2 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include TWI (Fm+ capable), USART1 XCK, SPI0 SCK, TCA0 WO2, EVSYS EVOUTC and LUT1 IN2.
19 PC3 bidirectional Multi-voltage I/O pin PC3 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include TWI (Fm+ capable), USART1 XDIR, SPI0 SS, TCA0 WO3 and LUT1 OUT.
20 VDDIO2 power_in Supply pin for the MVIO pin group on port C; it may be tied to VDD (single-supply mode) or driven at a separate voltage (dual-supply mode), per the MVIO section.
21 GND power_in Ground reference pin of the device; each supply pin pair needs its own decoupling capacitor.
22 PC4 bidirectional Multi-voltage I/O pin PC4 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART1 TxD, SPI1 MOSI and TCA0 WO4.
23 PC5 bidirectional Multi-voltage I/O pin PC5 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART1 RxD, SPI1 MISO and TCA0 WO5.
24 PC6 bidirectional Multi-voltage I/O pin PC6 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART1 XCK, SPI1 SCK, TWI SDA (slave), TCA0 WO2 and LUT1 OUT.
25 PC7 bidirectional Multi-voltage I/O pin PC7 on PORTC, powered from VDDIO2, with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART1 XDIR, SPI1 SS, TWI SCL (slave) and EVSYS EVOUTC.
26 PD0 bidirectional General-purpose bidirectional I/O pin PD0 on PORTD with configurable input buffer and pull-up; analog input AIN0 and LUT2 IN0 as listed in the I/O Multiplexing table.
27 PD1 bidirectional General-purpose bidirectional I/O pin PD1 on PORTD with configurable input buffer and pull-up; analog input AIN1, OP0 INP, ZCD0 ZCIN and LUT2 IN1 per the I/O Multiplexing table.
28 PD2 bidirectional General-purpose bidirectional I/O pin PD2 on PORTD with configurable input buffer and pull-up; analog input AIN2, OP0 OUT and EVSYS EVOUTD per the I/O Multiplexing table.
29 PD3 bidirectional General-purpose bidirectional I/O pin PD3 on PORTD with configurable input buffer and pull-up; analog input AIN3, OP0 INN and LUT2 OUT per the I/O Multiplexing table.
30 PD4 bidirectional General-purpose bidirectional I/O pin PD4 on PORTD with configurable input buffer and pull-up; analog input AIN4 and OP1 INP per the I/O Multiplexing table.
31 PD5 bidirectional General-purpose bidirectional I/O pin PD5 on PORTD with configurable input buffer and pull-up; analog input AIN5 and OP1 OUT per the I/O Multiplexing table.
32 PD6 bidirectional General-purpose bidirectional I/O pin PD6 on PORTD with configurable input buffer and pull-up; analog input AIN6, DAC0 output and LUT2 OUT per the I/O Multiplexing table.
33 PD7 bidirectional General-purpose bidirectional I/O pin PD7 on PORTD with configurable input buffer and pull-up; VREFA external voltage reference input, analog input AIN7, OP1 INN and EVSYS EVOUTD per the I/O Multiplexing table.
34 AVDD power_in Analog supply pin; the datasheet states AVDD is internally connected to VDD and is not a separate power domain on this family.
35 AGND power_in Analog ground pin of the device, shown as Ground in the pinout legend.
36 PE0 bidirectional General-purpose bidirectional I/O pin PE0 on PORTE with configurable input buffer and pull-up; analog input AIN8, USART4 TxD and SPI0 MOSI per the I/O Multiplexing table.
37 PE1 bidirectional General-purpose bidirectional I/O pin PE1 on PORTE with configurable input buffer and pull-up; analog input AIN9, OP2 INP, USART4 RxD and SPI0 MISO per the I/O Multiplexing table.
38 PE2 bidirectional General-purpose bidirectional I/O pin PE2 on PORTE with configurable input buffer and pull-up; analog input AIN10, OP2 OUT, USART4 XCK, SPI0 SCK and EVSYS EVOUTE per the I/O Multiplexing table.
39 PE3 bidirectional General-purpose bidirectional I/O pin PE3 on PORTE with configurable input buffer and pull-up; analog input AIN11, OP2 INN, ZCD1 ZCIN, USART4 XDIR and SPI0 SS per the I/O Multiplexing table.
40 PE4 bidirectional General-purpose bidirectional I/O pin PE4 on PORTE with configurable input buffer and pull-up; analog input AIN12, USART4 TxD and TCA0 WO4 per the I/O Multiplexing table.
41 PE5 bidirectional General-purpose bidirectional I/O pin PE5 on PORTE with configurable input buffer and pull-up; analog input AIN13, USART4 RxD and TCA0 WO5 per the I/O Multiplexing table.
42 PE6 bidirectional General-purpose bidirectional I/O pin PE6 on PORTE with configurable input buffer and pull-up; analog input AIN14, USART4 XCK and TCA0 WO2 per the I/O Multiplexing table.
43 PE7 bidirectional General-purpose bidirectional I/O pin PE7 on PORTE with configurable input buffer and pull-up; analog input AIN15, ZCD2 ZCIN, USART4 XDIR and EVSYS EVOUTE per the I/O Multiplexing table.
44 PF0 (XTAL32K1) bidirectional General-purpose bidirectional I/O pin PF0 on PORTF, also the XTAL32K1 connection for the 32.768 kHz crystal oscillator, with analog input AIN16 (not usable as a differential negative input).
45 PF1 (XTAL32K2) bidirectional General-purpose bidirectional I/O pin PF1 on PORTF, also the XTAL32K2 connection for the 32.768 kHz crystal oscillator, with analog input AIN17 (not usable as a differential negative input).
46 PF2 bidirectional General-purpose bidirectional I/O pin PF2 on PORTF with configurable input buffer and pull-up; analog input AIN18 (not usable as a differential negative input), TWI (Fm+ capable) and USART2 XCK.
47 PF3 bidirectional General-purpose bidirectional I/O pin PF3 on PORTF with configurable input buffer and pull-up; analog input AIN19 (not usable as a differential negative input), TWI (Fm+ capable) and USART2 XDIR.
48 PF4 bidirectional General-purpose bidirectional I/O pin PF4 on PORTF with configurable input buffer and pull-up; analog input AIN20 (not usable as a differential negative input) and USART2 TxD.
49 PF5 bidirectional General-purpose bidirectional I/O pin PF5 on PORTF with configurable input buffer and pull-up; analog input AIN21 (not usable as a differential negative input) and USART2 RxD.
50 PF6 input Input-only pin PF6 that serves as the RESET pin; the datasheet notes PF6/RESET is input only, and the external reset is enabled by the RSTPINCFG fuse with pull-up on PF6.
51 UPDI bidirectional Unified Program and Debug Interface pin used for one-wire half-duplex UART programming and debugging, with a dedicated pin with no other function.
52 PG0 bidirectional General-purpose bidirectional I/O pin PG0 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 TxD, TCA0 WO0 and LUT5 IN0.
53 PG1 bidirectional General-purpose bidirectional I/O pin PG1 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 RxD, TCA0 WO1 and LUT5 IN1.
54 PG2 bidirectional General-purpose bidirectional I/O pin PG2 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 XCK, TCA0 WO2, EVSYS EVOUTG and LUT5 IN2.
55 PG3 bidirectional General-purpose bidirectional I/O pin PG3 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 XDIR, TCA0 WO3 and LUT5 OUT.
56 VDD power_in Digital supply pin of the device; each VDD/GND pair needs its own decoupling capacitor placed close to the pins.
57 GND power_in Ground reference pin of the device; each supply pin pair needs its own decoupling capacitor.
58 PG4 bidirectional General-purpose bidirectional I/O pin PG4 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 TxD, SPI0 MOSI and TCA0 WOA.
59 PG5 bidirectional General-purpose bidirectional I/O pin PG5 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 RxD, SPI0 MISO and TCA0 WOB.
60 PG6 bidirectional General-purpose bidirectional I/O pin PG6 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 XCK, SPI0 SCK, TCA0 WOC and LUT5 OUT.
61 PG7 bidirectional General-purpose bidirectional I/O pin PG7 on PORTG with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include USART5 XDIR, SPI0 SS, TCA0 WOD and EVSYS EVOUTG.
62 PA0 (XTALHF1) bidirectional General-purpose bidirectional I/O pin PA0 on PORTA, also the XTALHF1 high-frequency crystal connection, with EXTCLK, USART0 TxD, TCA0 WO0 and LUT0 IN0 alternate functions per the I/O Multiplexing table.
63 PA1 (XTALHF2) bidirectional General-purpose bidirectional I/O pin PA1 on PORTA, also the XTALHF2 high-frequency crystal connection, with USART0 RxD, TCA0 WO1 and LUT0 IN1 alternate functions per the I/O Multiplexing table.
64 PA2 bidirectional General-purpose bidirectional I/O pin PA2 on PORTA with configurable input buffer and pull-up; alternate functions per the I/O Multiplexing table include TWI (Fm+ capable), USART0 XCK, TWI SDA (master/slave), TCA0 WO2, EVSYS EVOUTA and LUT0 IN2.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VDD, ordering table) 1.8 5.5 V Ordering information row AVR128DB64-I/PT, 64-pin TQFP, Supply Voltage column 629
Temperature range (ordering table) -40 85 °C Ordering information row AVR128DB64-I/PT, 64-pin TQFP, Temperature Range column (-40°C to +85°C) 629

CAD (KiCad official)

  • Symbol: AVR128DB64-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: avr128db64-i-pt-etched.step / avr128db64-i-pt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr128db64-i-pt.step / avr128db64-i-pt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (660 pp, sha256 1fb225fb44c6b2af, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF