component
AUN060N08AG
Public Made by Adomby adom
ANHI MOSFETs, DFN5x6-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AUN060N08AG
ANHI · MOSFETs · DFN5x6-8
AUN060N08AG from ANHI, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET, one of three source pins on the package bottom edge, tied together with pins 2 and 3. |
| 2 | S | passive | Source of the N-channel MOSFET, one of three source pins on the package bottom edge, tied together with pins 1 and 3. |
| 3 | S | passive | Source of the N-channel MOSFET, one of three source pins on the package bottom edge, tied together with pins 1 and 2. |
| 4 | G | input | Gate of the N-channel MOSFET, with a static VGS rating of ±20 V. |
| 5 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 6-8. |
| 6 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 5, 7 and 8. |
| 7 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 5, 6 and 8. |
| 8 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 5-7. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ANHI |
| Package | DFN5x6-8 |
| Category | Transistors/Thyristors |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source breakdown voltage | V(BR)DSS | 80 | V | VGS=0V, ID=10mA | 4 | ||
| Gate threshold voltage | V(GS)th | 2.5 | 3.4 | V | VDS=VGS, ID=250uA | 4 | |
| Zero gate voltage drain current | IDSS | 1000 | nA | VDS=80V, VGS=0V, Tj=25°C | 4 | ||
| Gate-source leakage current | IGSS | 100 | nA | VGS=20V, VDS=0V | 4 | ||
| Drain-source on-state resistance | RDS(on) | 5.4 | 6 | mΩ | VGS=10V, ID=20A, Tj=25°C | 4 | |
| Gate resistance (Intrinsic) | RG | 1.2 | Ω | f=1MHz, open drain | 4 | ||
| Continuous drain current | ID | 60 | A | TC=25°C | 2 | ||
| Pulsed drain current | ID,pulse | 240 | A | TC=25°C | 2 | ||
| Avalanche energy, single pulse | EAS | 300 | mJ | 2 | |||
| Gate source voltage (static) | VGS | -20 | 20 | V | static | 2 | |
| Power dissipation (DFN5x6) | Ptot | 74 | W | TC=25°C | 2 | ||
| Storage temperature | Tstg | -55 | 175 | °C | 2 | ||
| Operating junction temperature | Tj | -55 | 175 | °C | 2 | ||
| Thermal resistance, junction - case (DFN5x6) | RthJC | 1.7 | °C/W | 3 | |||
| Thermal resistance, junction - ambient (DFN5x6) | RthJA | 50 | °C/W | device on PCB, minimal footprint | 3 | ||
| Input capacitance | Ciss | 3730 | pF | Vds=40V,Vgs=0V f=1MHz | 4 | ||
| Output capacitance | Coss | 674 | pF | Vds=40V,Vgs=0V f=1MHz | 4 | ||
| Reverse transfer capacitance | Crss | 24.24 | pF | Vds=40V,Vgs=0V f=1MHz | 4 | ||
| Turn-on delay time | td(on) | 16.5 | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 | ||
| Rise time | tr | 13.7 | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 | ||
| Turn-off delay time | td(off) | 35.9 | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 | ||
| Fall time | tf | 13.45 | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 | ||
| Gate to source charge | Qgs | 15.9 | nC | VDS=40V,VGS=0 to 10V ID=20A | 4 | ||
| Gate to drain charge | Qgd | 13.3 | nC | VDS=40V,VGS=0 to 10V ID=20A | 4 | ||
| Gate charge total | Qg | 55.7 | nC | VDS=40V,VGS=0 to 10V ID=20A | 4 | ||
| Diode forward voltage | VSD | 0.7 | V | VGS=0V, IF=1A, Tj=25°C | 5 | ||
| Reverse recovery time | trr | 40.9 | ns | VR=40V,IF=20A, diF/dt=200A/us | 5 | ||
| Reverse recovery charge | Qrr | 106.8 | uC | VR=40V,IF=20A,diF/dt=200A/us | 5 | ||
| Peak reverse recovery current | Irrm | -3.7 | A | VR=40V,IF=20A,diF/dt=200A/us | 5 |
CAD (KiCad official)
- Symbol:
AUN060N08AG - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN5x6-8 (KiCad packages3D, STEP)
- 3D model files:
aun060n08ag-etched.step/aun060n08ag-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aun060n08ag.step/aun060n08ag.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ANHI datasheet (11 pp, sha256
edeb6312c3e9b47c, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AUN060N08AG
**ANHI** · MOSFETs · DFN5x6-8
AUN060N08AG from ANHI, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET, one of three source pins on the package bottom edge, tied together with pins 2 and 3. |
| 2 | S | passive | Source of the N-channel MOSFET, one of three source pins on the package bottom edge, tied together with pins 1 and 3. |
| 3 | S | passive | Source of the N-channel MOSFET, one of three source pins on the package bottom edge, tied together with pins 1 and 2. |
| 4 | G | input | Gate of the N-channel MOSFET, with a static VGS rating of ±20 V. |
| 5 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 6-8. |
| 6 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 5, 7 and 8. |
| 7 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 5, 6 and 8. |
| 8 | D | passive | Drain of the N-channel MOSFET (VDS 80 V), tied internally to the exposed drain pad and to pins 5-7. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ANHI |
| Package | DFN5x6-8 |
| Category | Transistors/Thyristors |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source breakdown voltage | V(BR)DSS | 80 | | | V | VGS=0V, ID=10mA | 4 |
| Gate threshold voltage | V(GS)th | 2.5 | | 3.4 | V | VDS=VGS, ID=250uA | 4 |
| Zero gate voltage drain current | IDSS | | | 1000 | nA | VDS=80V, VGS=0V, Tj=25°C | 4 |
| Gate-source leakage current | IGSS | | | 100 | nA | VGS=20V, VDS=0V | 4 |
| Drain-source on-state resistance | RDS(on) | | 5.4 | 6 | mΩ | VGS=10V, ID=20A, Tj=25°C | 4 |
| Gate resistance (Intrinsic) | RG | | 1.2 | | Ω | f=1MHz, open drain | 4 |
| Continuous drain current | ID | | | 60 | A | TC=25°C | 2 |
| Pulsed drain current | ID,pulse | | | 240 | A | TC=25°C | 2 |
| Avalanche energy, single pulse | EAS | | | 300 | mJ | | 2 |
| Gate source voltage (static) | VGS | -20 | | 20 | V | static | 2 |
| Power dissipation (DFN5x6) | Ptot | | | 74 | W | TC=25°C | 2 |
| Storage temperature | Tstg | -55 | | 175 | °C | | 2 |
| Operating junction temperature | Tj | -55 | | 175 | °C | | 2 |
| Thermal resistance, junction - case (DFN5x6) | RthJC | | | 1.7 | °C/W | | 3 |
| Thermal resistance, junction - ambient (DFN5x6) | RthJA | | | 50 | °C/W | device on PCB, minimal footprint | 3 |
| Input capacitance | Ciss | | 3730 | | pF | Vds=40V,Vgs=0V f=1MHz | 4 |
| Output capacitance | Coss | | 674 | | pF | Vds=40V,Vgs=0V f=1MHz | 4 |
| Reverse transfer capacitance | Crss | | 24.24 | | pF | Vds=40V,Vgs=0V f=1MHz | 4 |
| Turn-on delay time | td(on) | | 16.5 | | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 |
| Rise time | tr | | 13.7 | | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 |
| Turn-off delay time | td(off) | | 35.9 | | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 |
| Fall time | tf | | 13.45 | | ns | VDD=40V,VGS=10V,RG=10Ω ID=20A | 4 |
| Gate to source charge | Qgs | | 15.9 | | nC | VDS=40V,VGS=0 to 10V ID=20A | 4 |
| Gate to drain charge | Qgd | | 13.3 | | nC | VDS=40V,VGS=0 to 10V ID=20A | 4 |
| Gate charge total | Qg | | 55.7 | | nC | VDS=40V,VGS=0 to 10V ID=20A | 4 |
| Diode forward voltage | VSD | | 0.7 | | V | VGS=0V, IF=1A, Tj=25°C | 5 |
| Reverse recovery time | trr | | 40.9 | | ns | VR=40V,IF=20A, diF/dt=200A/us | 5 |
| Reverse recovery charge | Qrr | | 106.8 | | uC | VR=40V,IF=20A,diF/dt=200A/us | 5 |
| Peak reverse recovery current | Irrm | | -3.7 | | A | VR=40V,IF=20A,diF/dt=200A/us | 5 |
## CAD (KiCad official)
- Symbol: `AUN060N08AG`
- Footprint: `Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm`
- 3D model: DFN5x6-8 (KiCad packages3D, STEP)
- 3D model files: `aun060n08ag-etched.step` / `aun060n08ag-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aun060n08ag.step` / `aun060n08ag.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ANHI datasheet](docs/aun060n08ag-datasheet.pdf) (11 pp, sha256 `edeb6312c3e9b47c`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/aun060n08ag-datasheet.pdf)