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AUIRS2181STR
Public Made by Adomby adom
Infineon Technologies Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAUIRS2181STR
Infineon Technologies · Gate Drive ICs · SOIC-8
AUIRS2181STR from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HIN | input | Logic input for high-side gate driver output (HO), in phase; 3.3 V and 5 V logic compatible, referenced to COM/VSS. |
| 2 | LIN | input | Logic input for low-side driver output (LO), in phase; 3.3 V and 5 V logic compatible, referenced to COM/VSS. |
| 3 | COM | power_in | Low-side return and logic ground in the 8-lead package; no separate VSS pin on this package. |
| 4 | LO | output | Low-side gate drive output, swings from COM to VCC with 1.9 A source / 2.3 A sink typical. |
| 5 | VCC | power_in | Low-side and logic fixed supply, recommended 10 V to 20 V (absolute maximum 20 V). |
| 6 | VS | power_in | High-side floating supply return, offset up to 600 V recommended. |
| 7 | HO | output | High-side gate drive output, referenced to VS and swinging up to VB. |
| 8 | VB | power_in | High-side floating supply, VS+10 V to VS+20 V recommended, 625 V absolute maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side floating absolute voltage | VB | -0.3 | 625 | V | 4 | ||
| Low-side and logic fixed supply voltage | VCC | -0.3 | 20 | V | 4 | ||
| Low-side output voltage | VLO | -0.3 | V | 4 | |||
| Allowable offset supply voltage transient | dVS/dt | 50 | V/ns | 4 | |||
| Package power dissipation | PD | 0.625 | W | TA ≤ 25°C, 8 lead SOIC | 4 | ||
| Thermal resistance, junction to ambient | RthJA | 200 | °C/W | 8 lead SOIC | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | TS | -50 | 150 | °C | 4 | ||
| Lead temperature (soldering) | TL | 300 | °C | soldering, 10 seconds | 4 | ||
| High-side floating supply offset voltage | VS | 600 | V | 4 | |||
| Low-side and logic fixed supply voltage | VCC | 10 | 20 | V | 4 | ||
| Low-side output voltage | VLO | 0 | V | 4 | |||
| Logic ground | VSS | -5 | 5 | V | 4 | ||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Turn-on propagation delay | ton | 160 | 270 | ns | VS = 0 V | 5 | |
| Turn-off propagation delay | toff | 200 | 330 | ns | VS = 0 V or 600 V | 5 | |
| Delay matching, HS & LS turn-on/off | MT | 35 | ns | 5 | |||
| Turn-on rise time | tr | 15 | 60 | ns | VS = 0 V | 5 | |
| Turn-off fall time | tf | 15 | 35 | ns | 5 | ||
| Logic '1' input voltage | VIH | 2.5 | V | VCC = 10 V to 20 V | 5 | ||
| Logic '0' input voltage | VIL | 0.8 | V | VCC = 10 V to 20 V | 5 | ||
| High level output voltage, VBIAS - VO | VOH | 1.4 | V | IO = 0 mA | 5 | ||
| Low level output voltage, VO | VOL | 0.2 | V | IO = 20 mA | 5 | ||
| Offset supply leakage current | ILK | 50 | µA | VB = VS = 600 V | 5 | ||
| Quiescent VBS supply current | IQBS | 15 | 60 | 150 | µA | VIN = 0 V or 5 V | 5 |
| Quiescent VCC supply current | IQCC | 15 | 120 | 240 | µA | VIN = 0 V or 5 V | 5 |
| Logic '1' input bias current | IIN+ | 25 | 60 | µA | VIN = 5 V | 5 | |
| Logic '0' input bias current | IIN- | 5 | µA | VIN = 0 V | 5 | ||
| VCC and VBS supply undervoltage positive going threshold | VCCUV+, VBSUV+ | 8 | 8.9 | 9.8 | V | 5 | |
| VCC and VBS supply undervoltage negative going threshold | VCCUV-, VBSUV- | 7.4 | 8.2 | 9 | V | 5 | |
| VCC and VBS supply undervoltage hysteresis | VCCUVH, VBSUVH | 0.3 | 0.7 | V | 5 | ||
| Output high short circuit pulsed current | IO25+ | 1.4 | 1.9 | A | VO = 0V, PW ≤ 10us, TJ = 25°C | 5 | |
| Output low short circuit pulsed current | IO25- | 1.8 | 2.3 | A | VO = 15V, PW ≤ 10us, TJ = 25°C | 5 | |
| Output high short circuit pulsed current | IO+ | 1.2 | A | VO = 0 V, PW ≤ 10 us | 5 | ||
| Output low short circuit pulsed current | IO- | 1.5 | A | VO = 15 V, PW ≤ 10 us | 5 |
CAD (KiCad official)
- Symbol:
AUIRS2181STR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
auirs2181str-etched.step/auirs2181str-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);auirs2181str.step/auirs2181str.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (22 pp, sha256
48b21a6a17ffb5b1, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).