# ATTINY817-MNR

**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-24(4x4)

ATTINY817-MNR from Microchip Tech, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA2 | bidirectional | PORTA pin 2 general-purpose I/O with EVOUT0, AIN2 (ADC0), LUT0-IN2, SPI0 MISO, and alternate RxD/SCL positions. |
| 2 | PA3 | bidirectional | PORTA pin 3 general-purpose I/O that also serves as EXTCLK external clock input, AIN3 (ADC0), SPI0 SCK, TCA0 WO3, and alternate XCK. |
| 3 | GND | power_in | Ground; the datasheet also recommends soldering the large center pad to ground for mechanical stability. |
| 4 | VDD | power_in | Power supply pin; operating supply voltage is 1.8 V to 5.5 V. |
| 5 | PA4 | bidirectional | PORTA pin 4 general-purpose I/O with AIN4 (ADC0), PTC X0/Y0, SPI0 SS, TCA0 WO4, TCD0 WOA, LUT0-OUT, and alternate XDIR. |
| 6 | PA5 | bidirectional | PORTA pin 5 general-purpose I/O with AIN5 (ADC0), PTC X1/Y1, AC0 OUT, TCA0 WO5, TCB0 WO, and TCD0 WOB. |
| 7 | PA6 | bidirectional | PORTA pin 6 general-purpose I/O with AIN6 (ADC0), PTC X2/Y2, AC0 AINN0, and DAC0 OUT. |
| 8 | PA7 | bidirectional | PORTA pin 7 general-purpose I/O with AIN7 (ADC0), PTC X3/Y3, AC0 AINP0, and LUT1-OUT. |
| 9 | PB7 | bidirectional | PORTB pin 7 general-purpose I/O; no alternate function is listed for it in the multiplexing table. |
| 10 | PB6 | bidirectional | PORTB pin 6 general-purpose I/O; no alternate function is listed for it in the multiplexing table. |
| 11 | PB5 | bidirectional | PORTB pin 5 general-purpose I/O with CLKOUT, AIN8 (ADC0), AC0 AINP1, and alternate TCA0 WO2. |
| 12 | PB4 | bidirectional | PORTB pin 4 general-purpose I/O with AIN9 (ADC0), AC0 AINN1, and alternate TCA0 WO1 and LUT0-OUT. |
| 13 | PB3 | bidirectional | PORTB pin 3 general-purpose I/O that also serves as TOSC1 (32.768 kHz crystal), USART0 RxD, and alternate TCA0 WO0. |
| 14 | PB2 | bidirectional | PORTB pin 2 general-purpose I/O that also serves as TOSC2 (32.768 kHz crystal), EVOUT1, USART0 TxD, and TCA0 WO2. |
| 15 | PB1 | bidirectional | PORTB pin 1 general-purpose I/O with AIN10 (ADC0), PTC X4/Y4, USART0 XCK, TWI0 SDA, and TCA0 WO1. |
| 16 | PB0 | bidirectional | PORTB pin 0 general-purpose I/O with AIN11 (ADC0), PTC X5/Y5, USART0 XDIR, TWI0 SCL, and TCA0 WO0. |
| 17 | PC0 | bidirectional | PORTC pin 0 general-purpose I/O with TCD0 WOC and alternate SPI0 SCK and TCB0 WO. |
| 18 | PC1 | bidirectional | PORTC pin 1 general-purpose I/O with TCD0 WOD and alternate SPI0 MISO and LUT1-OUT. |
| 19 | PC2 | bidirectional | PORTC pin 2 general-purpose I/O with EVOUT2 and alternate SPI0 MOSI. |
| 20 | PC3 | bidirectional | PORTC pin 3 general-purpose I/O with LUT1-IN0 and alternate SPI0 SS and TCA0 WO3. |
| 21 | PC4 | bidirectional | PORTC pin 4 general-purpose I/O with LUT1-IN1 and alternate TCA0 WO4. |
| 22 | PC5 | bidirectional | PORTC pin 5 general-purpose I/O with LUT1-IN2 and alternate TCA0 WO5. |
| 23 | PA0 | bidirectional | PORTA pin 0 that serves as the RESET/UPDI programming and debug pin (function set by the RSTPINCFG fuse), with AIN0 (ADC0) and LUT0-IN0. |
| 24 | PA1 | bidirectional | PORTA pin 1 general-purpose I/O with AIN1 (ADC0), SPI0 MOSI, LUT0-IN1, and alternate TxD/SDA positions. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-24(4x4) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 1.8 |  | 5.5 | V | ATtiny817-MNR ordering table, supply voltage 1.8V-5.5V | 560 |
| Maximum CPU Speed |  |  |  | 20 | MHz | ATtiny817-MNR ordering table, max. CPU speed | 560 |
| Operating Temperature Range |  | -40 |  | 105 | °C | ATtiny817-MNR ordering table, temperature range | 560 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In the Self Capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. | 461 |

## CAD (KiCad official)

- Symbol: `ATTINY817-MNR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files: `attiny817-mnr-etched.step` / `attiny817-mnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `attiny817-mnr.step` / `attiny817-mnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/attiny817-mnr-datasheet.pdf) (596 pp, sha256 `c2392fe1c4c9666a`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/attiny817-mnr-datasheet.pdf)