ATTINY45-20SUR

{
  "slug": "attiny45-20sur",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "attiny45-20sur",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "attiny45-20sur.kicad_sym",
    "attiny45-20sur.kicad_mod",
    "attiny45-20sur.glb",
    "attiny45-20sur.step",
    "attiny45-20sur.lbr",
    "docs/hero.png",
    "docs/attiny45-20sur-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "attiny45-20sur-hero.glb",
    "attiny45-20sur-hero.overlay.json",
    "attiny45-20sur-etched.glb"
  ],
  "component": {
    "mpn": "ATTINY45-20SUR",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8-208mil",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586199984383803392",
    "parts": {
      "symbol": "attiny45-20sur.kicad_sym",
      "footprint": "attiny45-20sur.kicad_mod",
      "model_3d": "attiny45-20sur-hero.glb",
      "model_3d_plain": "attiny45-20sur-etched.glb",
      "model_3d_step": "attiny45-20sur-etched.step",
      "model_3d_step_plain": "attiny45-20sur.step",
      "lbr": "attiny45-20sur.lbr"
    },
    "distributor_links": {
      "lcsc": "C152211",
      "digikey": "ATTINY45-20SURTR-ND",
      "mouser": "556-ATTINY45-20SUR"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T17:27:51Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "ATTINY45-20SURTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "556-ATTINY45-20SUR",
        "status": "found",
        "lifecycle": "Not Recommended for New Designs"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "PB5",
        "type": "bidirectional",
        "description": "Port B bit 5 is a bidirectional I/O pin with a selectable internal pull-up that is tri-stated during reset; as RESET, a low level held longer than the minimum pulse length (Table 21-4, page 165) generates a device reset, and the pin can also be used as a weak I/O pin."
      },
      {
        "number": "2",
        "name": "PB3",
        "type": "bidirectional",
        "description": "Port B bit 3 is a bidirectional I/O pin with selectable internal pull-up that also serves as XTAL1/CLKI, OC1B and ADC3 alternate functions."
      },
      {
        "number": "3",
        "name": "PB4",
        "type": "bidirectional",
        "description": "Port B bit 4 is a bidirectional I/O pin with selectable internal pull-up that also serves as XTAL2/CLKO, OC1B and ADC2 alternate functions."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "5",
        "name": "PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)",
        "type": "bidirectional",
        "description": "Port B bit 0 is a bidirectional I/O pin with selectable internal pull-up that also serves as MOSI/DI/SDA, AIN0, OC0A, OC1A, AREF and PCINT0 alternate functions."
      },
      {
        "number": "6",
        "name": "PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)",
        "type": "bidirectional",
        "description": "Port B bit 1 is a bidirectional I/O pin with selectable internal pull-up that also serves as MISO/DO, AIN1, OC0B, OC1A and PCINT1 alternate functions."
      },
      {
        "number": "7",
        "name": "PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)",
        "type": "bidirectional",
        "description": "Port B bit 2 is a bidirectional I/O pin with selectable internal pull-up that also serves as SCK/USCK/SCL, ADC1, T0, INT0 and PCINT2 alternate functions."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage; the Features list gives 2.7 - 5.5 V for ATtiny45 (20 MHz speed grade at 4.5 - 5.5 V)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers were assigned from the text layout of the Figure 1-1 PDIP/SOIC/TSSOP drawing (left colum; The minimum RESET pulse length is referenced to Table 21-4 on page 165, which is not in the supplied; PB5 is typed bidirectional because it is a Port B pin that can also be used as an I/O. KiCad may cla"
        ],
        "pages_sent": 19,
        "cost_usd": 0.0772,
        "at": "2026-10-20T17:25:54"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586199984383803392",
        "pages": 30,
        "sha256": "80124a2d9a6f0385",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "attiny45-20sur.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "attiny45-20sur-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e1c7d48bfc0e8a36bb1f663d0f259a93d6781a46ecad129516d7806eff6d2971",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}