ATTINY412-SSNR

{
  "slug": "attiny412-ssnr",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "attiny412-ssnr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "attiny412-ssnr.kicad_sym",
    "attiny412-ssnr.kicad_mod",
    "attiny412-ssnr.glb",
    "attiny412-ssnr.step",
    "attiny412-ssnr.lbr",
    "docs/hero.png",
    "docs/attiny412-ssnr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "attiny412-ssnr-hero.glb",
    "attiny412-ssnr-hero.overlay.json",
    "attiny412-ssnr-etched.glb"
  ],
  "component": {
    "mpn": "ATTINY412-SSNR",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589012691923320832",
    "parts": {
      "symbol": "attiny412-ssnr.kicad_sym",
      "footprint": "attiny412-ssnr.kicad_mod",
      "model_3d": "attiny412-ssnr-hero.glb",
      "model_3d_plain": "attiny412-ssnr-etched.glb",
      "model_3d_step": "attiny412-ssnr-etched.step",
      "model_3d_step_plain": "attiny412-ssnr.step",
      "lbr": "attiny412-ssnr.lbr"
    },
    "distributor_links": {
      "lcsc": "C1337190",
      "digikey": "ATTINY412-SSNRTR-ND",
      "mouser": "556-ATTINY412-SSNR"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T00:03:37Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "ATTINY412-SSNRTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "556-ATTINY412-SSNR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage pin; the operating supply voltage is 2.7 V to 5.5 V (Table 36-2)."
      },
      {
        "number": "2",
        "name": "PA6",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA6, multiplexed in Table 5-2 to AIN6, AINN0, OUT, TxD, MOSI, WO0, WOA and LUT0-OUT, and usable as an external interrupt and event input."
      },
      {
        "number": "3",
        "name": "PA7",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA7, multiplexed in Table 5-2 to AIN7, AINP0, RxD, MISO, WO0, WOB and LUT1-OUT, and usable as an external interrupt and event input."
      },
      {
        "number": "4",
        "name": "PA1",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA1, multiplexed in Table 5-2 to AIN1, TxD, MOSI, SDA, WO1 and LUT0-IN1, and usable as an external interrupt and event input."
      },
      {
        "number": "5",
        "name": "PA2",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA2, multiplexed in Table 5-2 to EVOUT0, AIN2, RxD, MISO, SCL, WO2 and LUT0-IN2; PA2 has full asynchronous pin-change detection."
      },
      {
        "number": "6",
        "name": "PA0/RESET/UPDI",
        "type": "bidirectional",
        "description": "PA0 is multiplexed with AIN0, LUT0-IN0 and the RESET/UPDI function, which the RSTPINCFG fuse selects as GPIO, UPDI or RESET."
      },
      {
        "number": "7",
        "name": "PA3/EXTCLK",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA3, multiplexed in Table 5-2 to EXTCLK, AIN3, OUT, XCK, SCK and WO0/WO3, and usable as an external clock input."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference pin for the device."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN ATTINY412-SSNR does not appear in the supplied datasheet text. The 8-pin SOIC ordering codes; Table 5-2 (8-pin) does not map each function to a column unambiguously for PA6 and PA7. Pin descript; The 8-pin SOIC pinout is taken from section 4.1 and Table 5-2. The package dimensions are from drawi"
        ],
        "pages_sent": 91,
        "cost_usd": 0.3036,
        "at": "2026-10-18T00:01:42"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589012691923320832",
        "pages": 553,
        "sha256": "7cd19d54679f6f5a",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "attiny412-ssnr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "attiny412-ssnr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6cca752674a8b2f5b58fc97e7b27861d6205422c644d925deabccb228c1b15b8",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}