ATTINY412-SSF

{
  "slug": "attiny412-ssf",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "attiny412-ssf",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "attiny412-ssf.kicad_sym",
    "attiny412-ssf.kicad_mod",
    "attiny412-ssf.glb",
    "attiny412-ssf.step",
    "attiny412-ssf.lbr",
    "docs/hero.png",
    "docs/attiny412-ssf-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "attiny412-ssf-hero.glb",
    "attiny412-ssf-hero.overlay.json",
    "attiny412-ssf-etched.glb"
  ],
  "component": {
    "mpn": "ATTINY412-SSF",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589018528536412160",
    "parts": {
      "symbol": "attiny412-ssf.kicad_sym",
      "footprint": "attiny412-ssf.kicad_mod",
      "model_3d": "attiny412-ssf-hero.glb",
      "model_3d_plain": "attiny412-ssf-etched.glb",
      "model_3d_step": "attiny412-ssf-etched.step",
      "model_3d_step_plain": "attiny412-ssf.step",
      "lbr": "attiny412-ssf.lbr"
    },
    "distributor_links": {
      "lcsc": "C1338345",
      "digikey": "ATTINY412-SSF-ND",
      "mouser": "579-ATTINY412-SSF"
    },
    "distributor_check": {
      "checked_at": "2026-10-21T01:33:29Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "ATTINY412-SSF-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "579-ATTINY412-SSF",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Input supply pin; the operating supply voltage is 2.7 V to 5.5 V (Table 36-2)."
      },
      {
        "number": "2",
        "name": "PA6",
        "type": "bidirectional",
        "description": "Port A pin 6 general-purpose I/O, also providing ADC0 AIN6, AC0 AINN0 input, DAC0 OUT (PA6 is the DAC0 output pin), and alternate-position USART0 TxD and SPI0 MOSI functions."
      },
      {
        "number": "3",
        "name": "PA7",
        "type": "bidirectional",
        "description": "Port A pin 7 general-purpose I/O, also providing ADC0 AIN7, AC0 AINP0 input, alternate-position USART0 RxD and SPI0 MISO functions, and LUT1-OUT CCL output."
      },
      {
        "number": "4",
        "name": "PA1",
        "type": "bidirectional",
        "description": "Port A pin 1 general-purpose I/O, also providing ADC0 AIN1 input, USART0 TxD (alternate position), SPI0 MOSI, TWI0 SDA, and TCA0 WO1 output."
      },
      {
        "number": "5",
        "name": "PA2",
        "type": "bidirectional",
        "description": "Port A pin 2 general-purpose I/O, also providing EVSYS EVOUT0 event output, ADC0 AIN2 input, USART0 RxD (alternate position), SPI0 MISO, TWI0 SCL, and TCA0 WO2 output."
      },
      {
        "number": "6",
        "name": "PA0/RESET/UPDI",
        "type": "bidirectional",
        "description": "Port A pin 0 that is configured as RESET or UPDI by the RSTPINCFG fuse (GPIO, UPDI, or RESET), providing the single-pin Unified Program and Debug Interface when set to UPDI, and also ADC0 AIN0 input and CCL LUT0-IN0."
      },
      {
        "number": "7",
        "name": "PA3/EXTCLK",
        "type": "bidirectional",
        "description": "Port A pin 3 general-purpose I/O, also serving as the EXTCLK external clock input, ADC0 AIN3 input, USART0 XCK, SPI0 SCK, and TCA0 WO0/WO3 waveform output."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference pin for the device."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN ATTINY412-SSF does not appear in the datasheet ordering table. The 8-pin SOIC ordering codes; Pin 6 is PA0 with RESET/UPDI. Its function depends on the RSTPINCFG fuse setting (GPIO, UPDI, or RES; The per-pin voltage and current limits are not given in the pinout section. The only supply limit in"
        ],
        "pages_sent": 91,
        "cost_usd": 0.2942,
        "at": "2026-10-21T01:28:19"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589018528536412160",
        "pages": 553,
        "sha256": "7cd19d54679f6f5a",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "attiny412-ssf.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "attiny412-ssf-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "dceb8652b3c010c0cbf9bd93dff981f78f6595215e5cea0a61d83405e1f5e5da",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}