# ATTINY202-SSNR

**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · SOIC-8

ATTINY202-SSNR from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply voltage pin; the device operates from 1.8 V to 5.5 V (VDD operating supply voltage, Table 31-2). |
| 2 | PA6 | bidirectional | GPIO port A pin 6 with analog input AIN6 and AINN0, also carrying USART0 TxD, SPI0 MOSI (alternate position) and TCA0 WO0, and LUT0-OUT; alternate pin positions are selected through PORTMUX. |
| 3 | PA7 | bidirectional | GPIO port A pin 7 with analog input AIN7 and AINP0, also carrying USART0 RxD, SPI0 MISO (alternate position), TCA0 WO0 (alternate position) and LUT1-OUT; alternate pin positions are selected through PORTMUX. |
| 4 | PA1 | bidirectional | GPIO port A pin 1 with analog input AIN1, also carrying USART0 TxD (alternate position), SPI0 MOSI, TWI0 SDA, TCA0 WO1 and LUT0-IN1. |
| 5 | PA2 | bidirectional | GPIO port A pin 2 with analog input AIN2 and event output EVOUT0, also carrying USART0 RxD (alternate position), SPI0 MISO, TWI0 SCL, TCA0 WO2 and LUT0-IN2; this pin has full asynchronous external interrupt detection. |
| 6 | PA0 | bidirectional | GPIO port A pin 0 that doubles as the RESET/UPDI pin; RSTPINCFG fuse selects GPIO, UPDI or RESET, and 12 V on this pin can enable UPDI programming, with analog input AIN0, USART0 XDIR, SPI0 SS and LUT0-IN0 also available. |
| 7 | PA3 | bidirectional | GPIO port A pin 3 with analog input AIN3 and external clock input EXTCLK, also carrying USART0 XCK, SPI0 SCK, TCA0 WO0/WO3 and the CCL/USART OUT signal. |
| 8 | GND | power_in | Ground reference for the device. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |

## CAD (KiCad official)

- Symbol: `ATTINY202-SSNR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `attiny202-ssnr-etched.step` / `attiny202-ssnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `attiny202-ssnr.step` / `attiny202-ssnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589925599767519232) (544 pp, sha256 `e71a10c1ca3773a7`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/attiny202-ssnr-datasheet.pdf)