component
ATTINY13A-PU
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ATTINY13A-PU
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · DIP-8
ATTINY13A-PU from Microchip Tech, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB5 | bidirectional | Port B bit 5 is a bi-directional I/O pin with internal pull-up; as RESET it generates a device reset on a low level longer than the minimum pulse length (shorter pulses are not guaranteed to reset), and it can be used as a weak I/O pin. |
| 2 | PB3 | bidirectional | Port B bit 3 is a bi-directional I/O pin with internal pull-up, also serving as the CLKI clock input and ADC3 analog input. |
| 3 | PB4 | bidirectional | Port B bit 4 is a bi-directional I/O pin with internal pull-up, also serving as ADC2 analog input. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | PB0 (MOSI/AIN0/OC0A/PCINT0) | bidirectional | Port B bit 0 is a bi-directional I/O pin with internal pull-up and high sink/source capability, also serving as MOSI, AIN0 and OC0A alternate functions; it is tri-stated when reset is active. |
| 6 | PB1 (MISO/AIN1/OC0B/INT0/PCINT1) | bidirectional | Port B bit 1 is a bi-directional I/O pin with internal pull-up and high sink/source capability, also serving as MISO, AIN1, OC0B and INT0 alternate functions; it is tri-stated when reset is active. |
| 7 | PB2 (SCK/ADC1/T0/PCINT2) | bidirectional | Port B bit 2 is a bi-directional I/O pin with internal pull-up and high sink/source capability, also serving as SCK, ADC1 and T0 alternate functions; it is tri-stated when reset is active. |
| 8 | VCC | power_in | Supply voltage; the datasheet gives the operating voltage range as 1.8 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | -65 | 150 | °C | 117 | |||
| Operating Temperature (device absolute maximum range as printed) | -55 | 125 | °C | 117 | |||
| Voltage on any Pin except RESET with respect to Ground (printed upper limit VCC+0.5V) | -0.5 | V | 117 | ||||
| Voltage on RESET with respect to Ground | -0.5 | 13 | V | 117 | |||
| Maximum Operating Voltage | 6 | V | 117 | ||||
| DC Current per I/O Pin | 40 | mA | 117 | ||||
| DC Current VCC and GND Pins | 200 | mA | 117 | ||||
| Operating Voltage | VCC | 1.8 | 5.5 | V | 1 | ||
| Operating Temperature, Industrial range (ATtiny13A-PU) | -40 | 85 | °C | Industrial grade, -PU ordering code | 162 | ||
| Calibration Accuracy of Internal RC Oscillator, factory calibration | -10 | 10 | % | 4.8 / 9.6 MHz, VCC 3V, 25°C | 119 | ||
| Calibration Accuracy of Internal RC Oscillator, user calibration | -2 | 2 | % | Fixed frequency 4-5 / 8-10 MHz, fixed voltage 1.8-5.5V, fixed temperature -40 to +85°C | 119 | ||
| Input Low Voltage, Any Pin as I/O (printed max 0.2VCC) | VIL | -0.5 | V | VCC = 1.8 - 2.4V | 117 | ||
| Input Low Voltage, Any Pin as I/O (printed max 0.3VCC) | VIL | -0.5 | V | VCC = 2.4 - 5.5V | 117 | ||
| Input Low Voltage, RESET Pin as Reset (printed max 0.2VCC) | VIL | -0.5 | V | VCC = 1.8 - 5.5 | 117 | ||
| Output Low Voltage, Pins PB0 and PB1 | VOL | 0.8 | V | IOL = 20 mA, VCC = 5V | 117 | ||
| Output Low Voltage, Pins PB0 and PB1 | VOL | 0.6 | V | IOL = 10 mA, VCC = 3V | 117 | ||
| Output Low Voltage, Pins PB2, PB3 and PB4 | VOL | 0.8 | V | IOL = 10 mA, VCC = 5V | 117 | ||
| Output Low Voltage, Pins PB2, PB3 and PB4 | VOL | 0.6 | V | IOL = 5 mA, VCC = 3V | 117 | ||
| Output High Voltage, Pins PB0 and PB1 | VOH | 4 | V | IOH = -20 mA, VCC = 5V | 117 | ||
| Output High Voltage, Pins PB0 and PB1 | VOH | 2.3 | V | IOH = -10 mA, VCC = 3V | 117 | ||
| Output High Voltage, Pins PB2, PB3 and PB4 | VOH | 4.2 | V | IOH = -10 mA, VCC = 5V | 117 | ||
| Output High Voltage, Pins PB2, PB3 and PB4 | VOH | 2.5 | V | IOH = -5 mA, VCC = 3V | 117 | ||
| Input Leakage Current I/O Pin, pin low | ILIL | -1 | 1 | µA | VCC = 5.5V, pin low | 117 | |
| Input Leakage Current I/O Pin, pin high | ILIH | -1 | 1 | µA | VCC = 5.5V, pin high | 117 | |
| Pull-Up Resistor, I/O Pin | RPU | 20 | 50 | kΩ | VCC = 5.5V, input low | 117 | |
| Pull-Up Resistor, Reset Pin | RPU | 30 | 80 | kΩ | VCC = 5.5V, input low | 117 | |
| Supply Current, Active Mode | ICC | 0.2 | 0.35 | mA | f = 1MHz, VCC = 2V | 118 | |
| Supply Current, Active Mode | ICC | 1.2 | 1.8 | mA | f = 4MHz, VCC = 3V | 118 | |
| Supply Current, Active Mode | ICC | 3.6 | 6 | mA | f = 8MHz, VCC = 5V | 118 | |
| Supply Current, Idle Mode | ICC | 0.03 | 0.2 | mA | f = 1MHz, VCC = 2V | 118 | |
| Supply Current, Idle Mode | ICC | 0.2 | 1 | mA | f = 4MHz, VCC = 3V | 118 | |
| Supply Current, Idle Mode | ICC | 0.7 | 3 | mA | f = 8MHz, VCC = 5V | 118 | |
| Supply Current, Power-Down Mode | ICC | 3.9 | 10 | µA | WDT enabled, VCC = 3V | 118 | |
| Supply Current, Power-Down Mode | ICC | 0.15 | 2 | µA | WDT disabled, VCC = 3V | 118 | |
| Minimum pulse width on RESET Pin | tRST | 2000 | 2500 | ns | VCC = 1.8V | 120 | |
| Minimum pulse width on RESET Pin | tRST | 700 | 2500 | ns | VCC = 3V | 120 | |
| Minimum pulse width on RESET Pin | tRST | 400 | 2500 | ns | VCC = 5V | 120 | |
| Brown-out Detector Hysteresis | VHYST | 50 | mV | 120 | |||
| Min Pulse Width on Brown-out Reset | tBOD | 2 | µs | 120 | |||
| Internal bandgap reference voltage | VBG | 1 | 1.1 | 1.2 | V | VCC = 5V, TA = 25°C | 120 |
| Internal bandgap reference start-up time | tBG | 40 | 70 | µs | VCC = 5V, TA = 25°C | 120 | |
| Release threshold of power-on reset | VPOR | 1.1 | 1.4 | 1.6 | V | 120 | |
| Activation threshold of power-on reset | VPOA | 0.6 | 1.3 | 1.6 | V | 120 | |
| Power-On Slope Rate | SRON | 0.01 | V/ms | 120 | |||
| VBOT, BOD level fuse BODLEVEL[1:0] = 10 | VBOT | 1.7 | 1.8 | 2 | V | BODLEVEL[1:0] = 10 | 120 |
| VBOT, BOD level fuse BODLEVEL[1:0] = 01 | VBOT | 2.5 | 2.7 | 2.9 | V | BODLEVEL[1:0] = 01 | 120 |
| VBOT, BOD level fuse BODLEVEL[1:0] = 00 | VBOT | 4.1 | 4.3 | 4.5 | V | BODLEVEL[1:0] = 00 | 120 |
| Analog Comparator Input Offset Voltage | VAIO | 40 | mV | VCC = 5V, VIN = VCC / 2 | 121 | ||
| Analog Comparator Input Leakage Current | ILAC | -50 | 50 | nA | VCC = 5V, VIN = VCC / 2 | 121 | |
| Analog Propagation Delay (from saturation to slight overdrive) | tAPD | 750 | ns | VCC = 2.7V | 121 | ||
| Digital Propagation Delay | tDPD | 1 | 2 | CLK | VCC = 1.8 - 5.5V | 121 | |
| Absolute accuracy (incl. INL, DNL, quantization, gain and offset errors) | 3 | LSB | VREF = 4V, VCC = 4V, ADC clock = 200 kHz | 121 | |||
| Conversion Time, free running conversion | 13 | 260 | µs | Free running conversion | 121 | ||
| ADC Clock Frequency | 50 | 1000 | kHz | 121 | |||
| Internal Voltage Reference | VINT | 1 | 1.1 | 1.2 | V | 121 | |
| Clock Frequency (external clock drive) | 1/tCLCL | 0 | 4 | MHz | VCC = 1.8 - 5.5V | 119 | |
| Clock Frequency (external clock drive) | 1/tCLCL | 0 | 10 | MHz | VCC = 2.7 - 5.5V | 119 | |
| Clock Frequency (external clock drive) | 1/tCLCL | 0 | 20 | MHz | VCC = 4.5 - 5.5V | 119 | |
| High-voltage Reset: minimum High-voltage period for latching Prog_enable | tHVRST | 100 | ns | VCC = 4.5V | 111 | ||
| Clock Period (external clock drive) | tCLCL | 50 | ns | VCC = 4.5 - 5.5V | 119 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | , H or 7: NiPdAu lead finish, U, N or F: matte tin | 162 |
CAD (KiCad official)
- Symbol:
ATTINY13A-PU - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
attiny13a-pu-etched.step/attiny13a-pu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);attiny13a-pu.step/attiny13a-pu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (176 pp, sha256
f4501d963ad536b5, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATTINY13A-PU
**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · DIP-8
ATTINY13A-PU from Microchip Tech, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB5 | bidirectional | Port B bit 5 is a bi-directional I/O pin with internal pull-up; as RESET it generates a device reset on a low level longer than the minimum pulse length (shorter pulses are not guaranteed to reset), and it can be used as a weak I/O pin. |
| 2 | PB3 | bidirectional | Port B bit 3 is a bi-directional I/O pin with internal pull-up, also serving as the CLKI clock input and ADC3 analog input. |
| 3 | PB4 | bidirectional | Port B bit 4 is a bi-directional I/O pin with internal pull-up, also serving as ADC2 analog input. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | PB0 (MOSI/AIN0/OC0A/PCINT0) | bidirectional | Port B bit 0 is a bi-directional I/O pin with internal pull-up and high sink/source capability, also serving as MOSI, AIN0 and OC0A alternate functions; it is tri-stated when reset is active. |
| 6 | PB1 (MISO/AIN1/OC0B/INT0/PCINT1) | bidirectional | Port B bit 1 is a bi-directional I/O pin with internal pull-up and high sink/source capability, also serving as MISO, AIN1, OC0B and INT0 alternate functions; it is tri-stated when reset is active. |
| 7 | PB2 (SCK/ADC1/T0/PCINT2) | bidirectional | Port B bit 2 is a bi-directional I/O pin with internal pull-up and high sink/source capability, also serving as SCK, ADC1 and T0 alternate functions; it is tri-stated when reset is active. |
| 8 | VCC | power_in | Supply voltage; the datasheet gives the operating voltage range as 1.8 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | | -65 | | 150 | °C | | 117 |
| Operating Temperature (device absolute maximum range as printed) | | -55 | | 125 | °C | | 117 |
| Voltage on any Pin except RESET with respect to Ground (printed upper limit VCC+0.5V) | | -0.5 | | | V | | 117 |
| Voltage on RESET with respect to Ground | | -0.5 | | 13 | V | | 117 |
| Maximum Operating Voltage | | | | 6 | V | | 117 |
| DC Current per I/O Pin | | | | 40 | mA | | 117 |
| DC Current VCC and GND Pins | | | | 200 | mA | | 117 |
| Operating Voltage | VCC | 1.8 | | 5.5 | V | | 1 |
| Operating Temperature, Industrial range (ATtiny13A-PU) | | -40 | | 85 | °C | Industrial grade, -PU ordering code | 162 |
| Calibration Accuracy of Internal RC Oscillator, factory calibration | | -10 | | 10 | % | 4.8 / 9.6 MHz, VCC 3V, 25°C | 119 |
| Calibration Accuracy of Internal RC Oscillator, user calibration | | -2 | | 2 | % | Fixed frequency 4-5 / 8-10 MHz, fixed voltage 1.8-5.5V, fixed temperature -40 to +85°C | 119 |
| Input Low Voltage, Any Pin as I/O (printed max 0.2VCC) | VIL | -0.5 | | | V | VCC = 1.8 - 2.4V | 117 |
| Input Low Voltage, Any Pin as I/O (printed max 0.3VCC) | VIL | -0.5 | | | V | VCC = 2.4 - 5.5V | 117 |
| Input Low Voltage, RESET Pin as Reset (printed max 0.2VCC) | VIL | -0.5 | | | V | VCC = 1.8 - 5.5 | 117 |
| Output Low Voltage, Pins PB0 and PB1 | VOL | | | 0.8 | V | IOL = 20 mA, VCC = 5V | 117 |
| Output Low Voltage, Pins PB0 and PB1 | VOL | | | 0.6 | V | IOL = 10 mA, VCC = 3V | 117 |
| Output Low Voltage, Pins PB2, PB3 and PB4 | VOL | | | 0.8 | V | IOL = 10 mA, VCC = 5V | 117 |
| Output Low Voltage, Pins PB2, PB3 and PB4 | VOL | | | 0.6 | V | IOL = 5 mA, VCC = 3V | 117 |
| Output High Voltage, Pins PB0 and PB1 | VOH | 4 | | | V | IOH = -20 mA, VCC = 5V | 117 |
| Output High Voltage, Pins PB0 and PB1 | VOH | 2.3 | | | V | IOH = -10 mA, VCC = 3V | 117 |
| Output High Voltage, Pins PB2, PB3 and PB4 | VOH | 4.2 | | | V | IOH = -10 mA, VCC = 5V | 117 |
| Output High Voltage, Pins PB2, PB3 and PB4 | VOH | 2.5 | | | V | IOH = -5 mA, VCC = 3V | 117 |
| Input Leakage Current I/O Pin, pin low | ILIL | -1 | | 1 | µA | VCC = 5.5V, pin low | 117 |
| Input Leakage Current I/O Pin, pin high | ILIH | -1 | | 1 | µA | VCC = 5.5V, pin high | 117 |
| Pull-Up Resistor, I/O Pin | RPU | 20 | | 50 | kΩ | VCC = 5.5V, input low | 117 |
| Pull-Up Resistor, Reset Pin | RPU | 30 | | 80 | kΩ | VCC = 5.5V, input low | 117 |
| Supply Current, Active Mode | ICC | | 0.2 | 0.35 | mA | f = 1MHz, VCC = 2V | 118 |
| Supply Current, Active Mode | ICC | | 1.2 | 1.8 | mA | f = 4MHz, VCC = 3V | 118 |
| Supply Current, Active Mode | ICC | | 3.6 | 6 | mA | f = 8MHz, VCC = 5V | 118 |
| Supply Current, Idle Mode | ICC | | 0.03 | 0.2 | mA | f = 1MHz, VCC = 2V | 118 |
| Supply Current, Idle Mode | ICC | | 0.2 | 1 | mA | f = 4MHz, VCC = 3V | 118 |
| Supply Current, Idle Mode | ICC | | 0.7 | 3 | mA | f = 8MHz, VCC = 5V | 118 |
| Supply Current, Power-Down Mode | ICC | | 3.9 | 10 | µA | WDT enabled, VCC = 3V | 118 |
| Supply Current, Power-Down Mode | ICC | | 0.15 | 2 | µA | WDT disabled, VCC = 3V | 118 |
| Minimum pulse width on RESET Pin | tRST | 2000 | | 2500 | ns | VCC = 1.8V | 120 |
| Minimum pulse width on RESET Pin | tRST | 700 | | 2500 | ns | VCC = 3V | 120 |
| Minimum pulse width on RESET Pin | tRST | 400 | | 2500 | ns | VCC = 5V | 120 |
| Brown-out Detector Hysteresis | VHYST | | 50 | | mV | | 120 |
| Min Pulse Width on Brown-out Reset | tBOD | 2 | | | µs | | 120 |
| Internal bandgap reference voltage | VBG | 1 | 1.1 | 1.2 | V | VCC = 5V, TA = 25°C | 120 |
| Internal bandgap reference start-up time | tBG | | 40 | 70 | µs | VCC = 5V, TA = 25°C | 120 |
| Release threshold of power-on reset | VPOR | 1.1 | 1.4 | 1.6 | V | | 120 |
| Activation threshold of power-on reset | VPOA | 0.6 | 1.3 | 1.6 | V | | 120 |
| Power-On Slope Rate | SRON | 0.01 | | | V/ms | | 120 |
| VBOT, BOD level fuse BODLEVEL[1:0] = 10 | VBOT | 1.7 | 1.8 | 2 | V | BODLEVEL[1:0] = 10 | 120 |
| VBOT, BOD level fuse BODLEVEL[1:0] = 01 | VBOT | 2.5 | 2.7 | 2.9 | V | BODLEVEL[1:0] = 01 | 120 |
| VBOT, BOD level fuse BODLEVEL[1:0] = 00 | VBOT | 4.1 | 4.3 | 4.5 | V | BODLEVEL[1:0] = 00 | 120 |
| Analog Comparator Input Offset Voltage | VAIO | | | 40 | mV | VCC = 5V, VIN = VCC / 2 | 121 |
| Analog Comparator Input Leakage Current | ILAC | -50 | | 50 | nA | VCC = 5V, VIN = VCC / 2 | 121 |
| Analog Propagation Delay (from saturation to slight overdrive) | tAPD | | 750 | | ns | VCC = 2.7V | 121 |
| Digital Propagation Delay | tDPD | | 1 | 2 | CLK | VCC = 1.8 - 5.5V | 121 |
| Absolute accuracy (incl. INL, DNL, quantization, gain and offset errors) | | | | 3 | LSB | VREF = 4V, VCC = 4V, ADC clock = 200 kHz | 121 |
| Conversion Time, free running conversion | | 13 | | 260 | µs | Free running conversion | 121 |
| ADC Clock Frequency | | 50 | | 1000 | kHz | | 121 |
| Internal Voltage Reference | VINT | 1 | 1.1 | 1.2 | V | | 121 |
| Clock Frequency (external clock drive) | 1/tCLCL | 0 | | 4 | MHz | VCC = 1.8 - 5.5V | 119 |
| Clock Frequency (external clock drive) | 1/tCLCL | 0 | | 10 | MHz | VCC = 2.7 - 5.5V | 119 |
| Clock Frequency (external clock drive) | 1/tCLCL | 0 | | 20 | MHz | VCC = 4.5 - 5.5V | 119 |
| High-voltage Reset: minimum High-voltage period for latching Prog_enable | tHVRST | 100 | | | ns | VCC = 4.5V | 111 |
| Clock Period (external clock drive) | tCLCL | 50 | | | ns | VCC = 4.5 - 5.5V | 119 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin |, H or 7: NiPdAu lead finish, U, N or F: matte tin | 162 |
## CAD (KiCad official)
- Symbol: `ATTINY13A-PU`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files: `attiny13a-pu-etched.step` / `attiny13a-pu-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `attiny13a-pu.step` / `attiny13a-pu.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907152266711040) (176 pp, sha256 `f4501d963ad536b5`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/attiny13a-pu-datasheet.pdf)