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ATSAMV71Q21B-AABT
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Microchip Tech Pre-ordered MCUs, LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ATSAMV71Q21B-AABT
Microchip Tech · Pre-ordered MCUs · LQFP-144(20x20)
ATSAMV71Q21B-AABT from Microchip Tech, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD0 | bidirectional | PIO line on VDDIO (GPIO_AD) with extra DAC1, A GTXCK, B PWMC1_PWML0, C SPI1_NPCS1, D DCD0; resets as PIO input with pull-up and Schmitt trigger. |
| 2 | PD31 | bidirectional | PIO line on VDDIO with A QIO3, B UTXD3, C PCK2, D ISI_D11; resets as PIO input with pull-up and Schmitt trigger. |
| 3 | VDDOUT | power_out | Voltage regulator output on the VDDOUT power rail. |
| 4 | PE0 | bidirectional | PIO line on VDDIO with extra AFE1_AD11, A D8, B TIOA9, C I2SC1_WS; resets as PIO input with pull-up and Schmitt trigger. |
| 5 | VDDIN | power_in | Voltage regulator input, also supplying the ADC, DAC and analog comparator; must be at the same level as VDDIO. |
| 6 | PE1 | bidirectional | PIO line on VDDIO with A D9, B TIOB9, C I2SC1_DO; resets as PIO input with pull-up and Schmitt trigger. |
| 7 | PE2 | bidirectional | PIO line on VDDIO with A D10, B TCLK9, C I2SC1_DI; resets as PIO input with pull-up and Schmitt trigger. |
| 8 | VREFN | power_in | Negative reference voltage input for the analog converters, on the GND rail. |
| 9 | VREFP | power_in | Positive reference voltage input for the AFE and DAC, which must rise simultaneously with VDDIO and VDDIN. |
| 10 | PE3 | bidirectional | PIO line on VDDIO with extra AFE1_AD10, A D11, B TIOA10; resets as PIO input with pull-up and Schmitt trigger. |
| 11 | PC0 | bidirectional | PIO line on VDDIO with extra AFE1_AD9, A D0, B PWMC0_PWML0; resets as PIO input with pull-up and Schmitt trigger. |
| 12 | PC27 | bidirectional | PIO line on VDDIO with extra AFE1_AD8, A A9, B TIOB4, C SPI1_MOSI; resets as PIO input with pull-up and Schmitt trigger. |
| 13 | PC26 | bidirectional | PIO line on VDDIO with extra AFE1_AD7, A A8, B TIOA4, C SPI1_MISO; resets as PIO input with pull-up and Schmitt trigger. |
| 14 | PC31 | bidirectional | PIO line on VDDIO with extra AFE1_AD6, A A13, B TCLK5; resets as PIO input with pull-up and Schmitt trigger. |
| 15 | PC30 | bidirectional | PIO line on VDDIO with extra AFE1_AD5, A A12, B TIOB5, C SPI1_NPCS3; resets as PIO input with pull-up and Schmitt trigger. |
| 16 | PC29 | bidirectional | PIO line on VDDIO with extra AFE1_AD4, A A11, B TIOA5, C SPI1_NPCS2; resets as PIO input with pull-up and Schmitt trigger. |
| 17 | PC12 | bidirectional | PIO line on VDDIO with extra AFE1_AD3, A NCS3, B TIOB8, C CANRX1; resets as PIO input with pull-up and Schmitt trigger. |
| 18 | PC15 | bidirectional | PIO line on VDDIO with extra AFE1_AD2, A NCS1/SDCS, B PWMC0_PWML3; resets as PIO input with pull-up and Schmitt trigger. |
| 19 | PC13 | bidirectional | PIO line on VDDIO with extra AFE1_AD1, A NWAIT, B PWMC0_PWMH3; resets as PIO input with pull-up and Schmitt trigger. |
| 20 | PB1 | bidirectional | PIO line on VDDIO with extra AFE1_AD0/RTCOUT1, A PWMC0_PWMH1, B GTSUCOMP, C TXD0, D TK; resets as PIO input with pull-up and Schmitt trigger. |
| 21 | PB0 | bidirectional | PIO line on VDDIO with extra AFE0_AD10/RTCOUT0, A PWMC0_PWMH0, C RXD0, D TF; resets as PIO input with pull-up and Schmitt trigger. |
| 22 | PA20 | bidirectional | PIO line on VDDIO with extra AFE0_AD9/WKUP10, B PWMC0_PWML1, C A16, D I2SC1_CK; resets as PIO input with pull-up and Schmitt trigger. |
| 23 | PA19 | bidirectional | PIO line on VDDIO with extra AFE0_AD8/WKUP9, B PWMC0_PWML0, C A15, D I2SC1_MCK; resets as PIO input with pull-up and Schmitt trigger. |
| 24 | PA18 | bidirectional | PIO line on VDDIO with extra AFE0_AD7, A PWMC1_PWMEXTRG1, B PCK2, C A14; resets as PIO input with pull-up and Schmitt trigger. |
| 25 | PA17 | bidirectional | PIO line on VDDIO with extra AFE0_AD6, A QIO2, B PCK1, C PWMC0_PWMH3; resets as PIO input with pull-up and Schmitt trigger. |
| 26 | PB2 | bidirectional | PIO line on VDDIO with extra AFE0_AD5, A CANTX0, C CTS0, D SPI0_NPCS0; resets as PIO input with pull-up and Schmitt trigger. |
| 27 | PE4 | bidirectional | PIO line on VDDIO with extra AFE0_AD4, A D12, B TIOB10; resets as PIO input with pull-up and Schmitt trigger. |
| 28 | PE5 | bidirectional | PIO line on VDDIO with extra AFE0_AD3, A D13, B TCLK10; resets as PIO input with pull-up and Schmitt trigger. |
| 29 | VDDCORE | power_in | Core supply powering the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 30 | VDDIO | power_in | Supply for peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads; 3.0V to 3.6V for USB operation. |
| 31 | PB3 | bidirectional | PIO line on VDDIO with extra AFE0_AD2/WKUP12, A CANRX0, B PCK2, C RTS0, D ISI_D2; resets as PIO input with pull-up and Schmitt trigger. |
| 32 | PA21 | bidirectional | PIO line on VDDIO with extra AFE0_AD1/PIODCEN2, A RXD1, B PCK1, C PWMC1_PWMFI0; resets as PIO input with pull-up and Schmitt trigger. |
| 33 | VDDCORE | power_in | Core supply powering the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 34 | PD30 | bidirectional | PIO line on VDDIO with extra AFE0_AD0, A UTXD3, D ISI_D10; resets as PIO input with pull-up and Schmitt trigger. |
| 35 | PA7 | bidirectional | Clock-type PIO line on VDDIO with extra XIN32 (32.768 kHz oscillator input) and B PWMC0_PWMH3; resets as PIO in HiZ. |
| 36 | PA8 | bidirectional | Clock-type PIO line on VDDIO with extra XOUT32 (32.768 kHz oscillator output), A PWMC1_PWMH3, B AFE0_ADTRG; resets as PIO in HiZ. |
| 37 | PA22 | bidirectional | PIO line on VDDIO with extra PIODCCLK, A RK, B PWMC0_PWMEXTRG1, C NCS2; resets as PIO input with pull-up and Schmitt trigger. |
| 38 | PC1 | bidirectional | PIO line on VDDIO with A D1, B PWMC0_PWML1; resets as PIO input with pull-up and Schmitt trigger. |
| 39 | PC2 | bidirectional | PIO line on VDDIO with A D2, B PWMC0_PWML2; resets as PIO input with pull-up and Schmitt trigger. |
| 40 | PC3 | bidirectional | PIO line on VDDIO with A D3, B PWMC0_PWML3; resets as PIO input with pull-up and Schmitt trigger. |
| 41 | PC4 | bidirectional | PIO line on VDDIO with A D4; resets as PIO input with pull-up and Schmitt trigger. |
| 42 | PA13 | bidirectional | PIO line on VDDIO with extra PIODC7, A QIO0, B PWMC0_PWMH2, C PWMC1_PWML1; resets as PIO input with pull-up and Schmitt trigger. |
| 43 | VDDIO | power_in | Supply for peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads; 3.0V to 3.6V for USB operation. |
| 44 | GND | power_in | Ground for the voltage regulator, core and peripheral I/O lines. |
| 45 | PA16 | bidirectional | PIO line on VDDIO with A D15, B TIOB1, C PWMC0_PWML2, D I2SC0_DI; resets as PIO input with pull-up and Schmitt trigger. |
| 46 | PA23 | bidirectional | PIO line on VDDIO with A SCK1, B PWMC0_PWMH0, C A19, D PWMC1_PWML2; resets as PIO input with pull-up and Schmitt trigger. |
| 47 | PD27 | bidirectional | PIO line on VDDIO with A PWMC0_PWML3, B SPI0_NPCS3, C TWD2, D ISI_D8; resets as PIO input with pull-up and Schmitt trigger. |
| 48 | PC7 | bidirectional | PIO line on VDDIO with A D7, B TCLK6; resets as PIO input with pull-up and Schmitt trigger. |
| 49 | PA15 | bidirectional | PIO line on VDDIO with A D14, B TIOA1, C PWMC0_PWML3, D I2SC0_WS; resets as PIO input with pull-up and Schmitt trigger. |
| 50 | VDDCORE | power_in | Core supply powering the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 51 | PA14 | bidirectional | Clock-type PIO line on VDDIO with extra WKUP8/PIODCEN1, A QSCK, B PWMC0_PWMH3, C PWMC1_PWMH1; resets as PIO input with pull-up and Schmitt trigger. |
| 52 | PD25 | bidirectional | PIO line on VDDIO with A PWMC0_PWML1, B SPI0_NPCS1, C URXD2, D ISI_VSYNC; resets as PIO input with pull-up and Schmitt trigger. |
| 53 | PD26 | bidirectional | PIO line on VDDIO with A PWMC0_PWML2, B TD, C UTXD2, D UTXD1; resets as PIO input with pull-up and Schmitt trigger. |
| 54 | PC6 | bidirectional | PIO line on VDDIO with A D6, B TIOB6; resets as PIO input with pull-up and Schmitt trigger. |
| 55 | PD24 | bidirectional | PIO line on VDDIO with A PWMC0_PWML0, B RF, C TCLK11, D ISI_HSYNC; resets as PIO input with pull-up and Schmitt trigger. |
| 56 | PA24 | bidirectional | PIO line on VDDIO with A RTS1, B PWMC0_PWMH1, C A20, D ISI_PCK; resets as PIO input with pull-up and Schmitt trigger. |
| 57 | PD23 | bidirectional | Clock-type PIO line on VDDIO with A PWMC0_PWMH3; resets as PIO input with pull-up and Schmitt trigger. |
| 58 | PC5 | bidirectional | PIO line on VDDIO with A D5, B TIOA6; resets as PIO input with pull-up and Schmitt trigger. |
| 59 | PA25 | bidirectional | PIO line on VDDIO with A CTS1, B PWMC0_PWMH2, C A23, D MCCK; resets as PIO input with pull-up and Schmitt trigger. |
| 60 | PD22 | bidirectional | PIO line on VDDIO with A PWMC0_PWMH2, B SPI0_SPCK, C TIOB11, D ISI_D0; resets as PIO input with pull-up and Schmitt trigger. |
| 61 | GND | power_in | Ground for the voltage regulator, core and peripheral I/O lines. |
| 62 | PA26 | bidirectional | PIO line on VDDIO with A DCD1, B TIOA2, C MCDA2, D PWMC1_PWMFI1; resets as PIO input with pull-up and Schmitt trigger. |
| 63 | PD21 | bidirectional | PIO line on VDDIO with A PWMC0_PWMH1, B SPI0_MOSI, C TIOA11, D ISI_D1; resets as PIO input with pull-up and Schmitt trigger. |
| 64 | PA11 | bidirectional | PIO line on VDDIO with extra WKUP7/PIODC5, A QCS, B PWMC0_PWMH0, C PWMC1_PWML0; resets as PIO input with pull-up and Schmitt trigger. |
| 65 | PD20 | bidirectional | PIO line on VDDIO with A PWMC0_PWMH0, B SPI0_MISO, C GTSUCOMP; resets as PIO input with pull-up and Schmitt trigger. |
| 66 | PA10 | bidirectional | PIO line on VDDIO with extra PIODC4, A UTXD0, B PWMC0_PWMEXTRG0, C RD; resets as PIO input with pull-up and Schmitt trigger. |
| 67 | PD19 | bidirectional | PIO line on VDDIO with A NCS3, B CTS2, C UTXD4; resets as PIO input with pull-up and Schmitt trigger. |
| 68 | PA12 | bidirectional | PIO line on VDDIO with extra PIODC6, A QIO1, B PWMC0_PWMH1, C PWMC1_PWMH0; resets as PIO input with pull-up and Schmitt trigger. |
| 69 | PD18 | bidirectional | PIO line on VDDIO with A NCS1/SDCS, B RTS2, C URXD4; resets as PIO input with pull-up and Schmitt trigger. |
| 70 | PA27 | bidirectional | PIO line on VDDIO with A DTR1, B TIOB2, C MCDA3, D ISI_D7; resets as PIO input with pull-up and Schmitt trigger. |
| 71 | PD28 | bidirectional | PIO line on VDDIO with extra WKUP5, A URXD3, C TWCK2, D ISI_D9; resets as PIO input with pull-up and Schmitt trigger. |
| 72 | VDDIO | power_in | Supply for peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads; 3.0V to 3.6V for USB operation. |
| 73 | PA5 | bidirectional | PIO line on VDDIO with extra WKUP4/PIODC2, A PWMC1_PWML3, B ISI_D4, C URXD1; resets as PIO input with pull-up and Schmitt trigger. |
| 74 | PD17 | bidirectional | PIO line on VDDIO with A GTXER, B SCK2; resets as PIO input with pull-up and Schmitt trigger. |
| 75 | PA9 | bidirectional | PIO line on VDDIO with extra WKUP6/PIODC3, A URXD0, B ISI_D3, C PWMC0_PWMFI0; resets as PIO input with pull-up and Schmitt trigger. |
| 76 | PC28 | bidirectional | PIO line on VDDIO with A A10, B TCLK4, C SPI1_NPCS1; resets as PIO input with pull-up and Schmitt trigger. |
| 77 | PA4 | bidirectional | PIO line on VDDIO with extra WKUP3/PIODC1, A TWCK0, B TCLK0, C UTXD1; resets as PIO input with pull-up and Schmitt trigger. |
| 78 | PD16 | bidirectional | PIO line on VDDIO with A GTX3, B TXD2; resets as PIO input with pull-up and Schmitt trigger. |
| 79 | PB6 | bidirectional | System I/O line on VDDIO whose default function is SWDIO/TMS (serial wire debug I/O / test mode select), selectable via CCFG_SYSIO; resets as PIO input with Schmitt trigger. |
| 80 | VDDIO | power_in | Supply for peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads; 3.0V to 3.6V for USB operation. |
| 81 | VDDCORE | power_in | Core supply powering the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 82 | PC8 | bidirectional | PIO line on VDDIO with A NWR0/NWE, B TIOA7; resets as PIO input with pull-up and Schmitt trigger. |
| 83 | NRST | bidirectional | Active-low microcontroller reset input/output on VDDIO; resets as input with pull-up. |
| 84 | PD14 | bidirectional | PIO line on VDDIO with A GRXCK; resets as PIO input with pull-up and Schmitt trigger. |
| 85 | TST | input | Test select input for JTAG boundary scan manufacturing test or Fast Flash Programming mode, with a permanent pulldown of about 15 kOhm to GND so it can be left unconnected in normal operation. |
| 86 | PC9 | bidirectional | PIO line on VDDIO with A NANDOE, B TIOB7; resets as PIO input with pull-up and Schmitt trigger. |
| 87 | PB12 | bidirectional | PIO line on VDDIO with extra ERASE, A PWMC0_PWML1, B GTSUCOMP, D PCK0; resets as PIO input with pull-down and Schmitt trigger. |
| 88 | PD13 | bidirectional | Clock-type PIO line on VDDIO with A GCOL; resets as PIO input with pull-up and Schmitt trigger. |
| 89 | PB7 | bidirectional | System I/O line on VDDIO whose default function is SWCLK/TCK (serial wire clock / test clock), selectable via CCFG_SYSIO; resets as PIO input with Schmitt trigger. |
| 90 | PC10 | bidirectional | PIO line on VDDIO with A NANDWE, B TCLK7; resets as PIO input with pull-up and Schmitt trigger. |
| 91 | PA3 | bidirectional | PIO line on VDDIO with extra PIODC0, A TWD0, B LONCOL1, C PCK2; resets as PIO input with pull-up and Schmitt trigger. |
| 92 | PD12 | bidirectional | PIO line on VDDIO with A GRX3, B CANTX1, C SPI0_NPCS2, D ISI_D6; resets as PIO input with pull-up and Schmitt trigger. |
| 93 | PA2 | bidirectional | PIO line on VDDIO with extra WKUP2, A PWMC0_PWMH1, C DATRG; resets as PIO input with pull-up and Schmitt trigger. |
| 94 | PC11 | bidirectional | PIO line on VDDIO with A NRD, B TIOA8; resets as PIO input with pull-up and Schmitt trigger. |
| 95 | GND | power_in | Ground for the voltage regulator, core and peripheral I/O lines. |
| 96 | VDDIO | power_in | Supply for peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads; 3.0V to 3.6V for USB operation. |
| 97 | PC14 | bidirectional | PIO line on VDDIO with A NCS0, B TCLK8, C CANTX1; resets as PIO input with pull-up and Schmitt trigger. |
| 98 | PD11 | bidirectional | PIO line on VDDIO with A GRX2, B PWMC0_PWMH0, C GTSUCOMP, D ISI_D5; resets as PIO input with pull-up and Schmitt trigger. |
| 99 | PA1 | bidirectional | PIO line on VDDIO with extra WKUP1, A PWMC0_PWML0, B TIOB0, C A18, D I2SC0_CK; resets as PIO input with pull-up and Schmitt trigger. |
| 100 | PC16 | bidirectional | PIO line on VDDIO with A A21/NANDALE; resets as PIO input with pull-up and Schmitt trigger. |
| 101 | PD10 | bidirectional | MLB-type PIO line on VDDIO with A GCRS, B PWMC0_PWML0, C TD, D MLBSIG; resets as PIO input with pull-down and Schmitt trigger. |
| 102 | PA0 | bidirectional | PIO line on VDDIO with extra WKUP0, A PWMC0_PWMH0, B TIOA0, C A17, D I2SC0_MCK; resets as PIO input with pull-up and Schmitt trigger. |
| 103 | PC17 | bidirectional | PIO line on VDDIO with A A22/NANDCLE; resets as PIO input with pull-up and Schmitt trigger. |
| 104 | JTAGSEL | input | JTAG selection input, active high, selecting JTAG boundary scan when high, with a permanent pulldown of about 15 kOhm to GND so it can be left unconnected in normal operation. |
| 105 | PB4 | bidirectional | MLB-type PIO line on VDDIO with extra TDI, A TWD1, B PWMC0_PWMH2, C MLBCLK, D TXD1; resets as PIO input with pull-up and Schmitt trigger. |
| 106 | PD15 | bidirectional | PIO line on VDDIO with A GTX2, B RXD2, C NWR1/NBS1; resets as PIO input with pull-up and Schmitt trigger. |
| 107 | VDDCORE | power_in | Core supply powering the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 108 | PD29 | bidirectional | PIO line on VDDIO with no alternate or peripheral function listed; resets as PIO input with pull-up and Schmitt trigger. |
| 109 | PB5 | bidirectional | MLB-type PIO line on VDDIO with extra TDO/TRACESWO/WKUP13, A TWCK1, B PWMC0_PWML0, C MLBDAT, D TD; resets as output with pull-up. |
| 110 | PD9 | bidirectional | Clock-type PIO line on VDDIO with A GMDIO, B PWMC0_PWMFI2, C AFE1_ADTRG; resets as PIO input with pull-up and Schmitt trigger. |
| 111 | PC18 | bidirectional | PIO line on VDDIO with A A0/NBS0, B PWMC0_PWML1; resets as PIO input with pull-up and Schmitt trigger. |
| 112 | PA28 | bidirectional | PIO line on VDDIO with A DSR1, B TCLK1, C MCCDA, D PWMC1_PWMFI2; resets as PIO input with pull-up and Schmitt trigger. |
| 113 | PD8 | bidirectional | Clock-type PIO line on VDDIO with A GMDC, B PWMC0_PWMFI1, D TRACECLK; resets as PIO input with pull-up and Schmitt trigger. |
| 114 | PA6 | bidirectional | PIO line on VDDIO with B PCK0, C UTXD1; resets as PIO input with pull-up and Schmitt trigger. |
| 115 | GND | power_in | Ground for the voltage regulator, core and peripheral I/O lines. |
| 116 | PA30 | bidirectional | PIO line on VDDIO with extra WKUP11, A PWMC0_PWML2, B PWMC1_PWMEXTRG0, C MCDA0, D I2SC0_DO; resets as PIO input with pull-up and Schmitt trigger. |
| 117 | PC19 | bidirectional | PIO line on VDDIO with A A1, B PWMC0_PWMH2; resets as PIO input with pull-up and Schmitt trigger. |
| 118 | PA31 | bidirectional | PIO line on VDDIO with A SPI0_NPCS1, B PCK2, C MCDA1, D PWMC1_PWMH2; resets as PIO input with pull-up and Schmitt trigger. |
| 119 | PD7 | bidirectional | Clock-type PIO line on VDDIO with A GRXER, B PWMC1_PWMH3, C TRACED3, D RI2; resets as PIO input with pull-up and Schmitt trigger. |
| 120 | PC20 | bidirectional | PIO line on VDDIO with A A2, B PWMC0_PWML2; resets as PIO input with pull-up and Schmitt trigger. |
| 121 | PD6 | bidirectional | Clock-type PIO line on VDDIO with A GRX1, B PWMC1_PWML3, C TRACED2, D DSR2; resets as PIO input with pull-up and Schmitt trigger. |
| 122 | PC21 | bidirectional | PIO line on VDDIO with A A3, B PWMC0_PWMH3; resets as PIO input with pull-up and Schmitt trigger. |
| 123 | VDDPLL | power_in | Supply for PLLA and the fast RC oscillator; its level must not vary more than 0.6V from VDDCORE. |
| 124 | PC22 | bidirectional | PIO line on VDDIO with A A4, B PWMC0_PWML3; resets as PIO input with pull-up and Schmitt trigger. |
| 125 | PD5 | bidirectional | Clock-type PIO line on VDDIO with A GRX0, B PWMC1_PWMH2, C TRACED1, D DTR2; resets as PIO input with pull-up and Schmitt trigger. |
| 126 | PD4 | bidirectional | Clock-type PIO line on VDDIO with A GRXDV, B PWMC1_PWML2, C TRACED0, D DCD2; resets as PIO input with pull-up and Schmitt trigger. |
| 127 | PC23 | bidirectional | PIO line on VDDIO with A A5, B TIOA3; resets as PIO input with pull-up and Schmitt trigger. |
| 128 | PD3 | bidirectional | PIO line on VDDIO with A GTX1, B PWMC1_PWMH1, C UTXD4, D RI0; resets as PIO input with pull-up and Schmitt trigger. |
| 129 | PA29 | bidirectional | PIO line on VDDIO with A RI1, B TCLK2; resets as PIO input with pull-up and Schmitt trigger. |
| 130 | PC24 | bidirectional | PIO line on VDDIO with A A6, B TIOB3, C SPI1_SPCK; resets as PIO input with pull-up and Schmitt trigger. |
| 131 | PD2 | bidirectional | PIO line on VDDIO with A GTX0, B PWMC1_PWML1, C SPI1_NPCS3, D DSR0; resets as PIO input with pull-up and Schmitt trigger. |
| 132 | PD1 | bidirectional | PIO line on VDDIO with A GTXEN, B PWMC1_PWMH0, C SPI1_NPCS2, D DTR0; resets as PIO input with pull-up and Schmitt trigger. |
| 133 | PC25 | bidirectional | PIO line on VDDIO with A A7, B TCLK3, C SPI1_NPCS0; resets as PIO input with pull-up and Schmitt trigger. |
| 134 | VDDUTMII | power_in | USB transceiver interface supply that must be connected to VDDIO and be 3.0V to 3.6V for USB operation. |
| 135 | GND | power_in | Ground for the voltage regulator, core and peripheral I/O lines. |
| 136 | HSDM | bidirectional | USB high-speed data minus line (D-) on the VDDUTMII rail. |
| 137 | HSDP | bidirectional | USB high-speed data plus line (D+) on the VDDUTMII rail. |
| 138 | GND | power_in | Ground for the voltage regulator, core and peripheral I/O lines. |
| 139 | VDDUTMIC | power_in | USB transceiver core supply, which must always be connected even if USB is not used, with its level within 0.6V of VDDCORE. |
| 140 | VBG | passive | Bandgap voltage pin listed as an input with no further function described. |
| 141 | PB8 | bidirectional | Clock-type PIO line on VDDIO with extra XOUT (main crystal oscillator output); resets as PIO in HiZ. |
| 142 | PB9 | bidirectional | Clock-type PIO line on VDDIO with extra XIN (main crystal oscillator input); resets as PIO in HiZ. |
| 143 | VDDPLLUSB | power_in | Supply for the UTMI PLL and the 3 MHz to 20 MHz oscillator; must be 3.0V or higher for USB operation. |
| 144 | PB13 | bidirectional | PIO line on VDDIO with extra DAC0 output, A PWMC0_PWML2, B PCK0, C SCK0; resets as PIO input with pull-up and Schmitt trigger. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | LQFP-144(20x20) |
| Category | Embedded Processors & Controllers |
| Pins | 144 |
CAD (KiCad official)
- Symbol:
ATSAMV71Q21B-AABT - Footprint:
Package_QFP:LQFP-144_20x20mm_P0.5mm - 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
- 3D model files:
atsamv71q21b-aabt-etched.step/atsamv71q21b-aabt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atsamv71q21b-aabt.step/atsamv71q21b-aabt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (1943 pp, sha256
94ed9d6997caca1c, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).