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ATSAMR21G18A-MU
Public Made by Adomby adom
Microchip Tech MICROCHIP, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ATSAMR21G18A-MU
Microchip Tech · MICROCHIP · QFN-48-EP(7x7)
ATSAMR21G18A-MU from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA00 | bidirectional | General-purpose I/O on VDDANA supply; XIN32 32kHz crystal input, EXTINT none, SERCOM1/PAD[0], TCC2/WO[0]. |
| 2 | PA01 | bidirectional | General-purpose I/O on VDDANA supply; XOUT32 32kHz crystal output, EXTINT[1], SERCOM1/PAD[1], TCC2/WO[1]. |
| 3 | XTAL2 | output | Output of the AT86RF233 16MHz reference crystal oscillator amplifier (XOSCRF); DC level 0.9V. |
| 4 | XTAL1 | input | Input of the 16MHz reference crystal oscillator amplifier (XOSCRF), also the input for an external clock reference; DC level 0.9V. |
| 5 | GNDANA | power_in | Ground for the analog power domain. |
| 6 | VDDANA | power_in | Analog supply, 1.8V to 3.6V, with 100nF and 10µF decoupling (optionally via ferrite bead). |
| 7 | AVDD | power_out | Output of the internal analog 1.8V voltage regulator for the radio; requires 100nF bypass capacitor. |
| 8 | GNDANA | power_in | Ground for the analog power domain. |
| 9 | PA04 | bidirectional | General-purpose I/O on VDDANA; EXTINT[4], ADC VREFB/AIN[4], AC AIN[0], PTC Y[2], SERCOM0/PAD[0], TCC0/WO[0]. |
| 10 | PA05 | bidirectional | General-purpose I/O on VDDANA; EXTINT[5], ADC AIN[5], AC AIN[1], PTC Y[3], SERCOM0/PAD[1], TCC0/WO[1]. |
| 11 | PA06 | bidirectional | General-purpose I/O on VDDANA; EXTINT[6], ADC AIN[6], AC AIN[2], PTC Y[4], SERCOM0/PAD[2], TCC1/WO[0]. |
| 12 | PA07 | bidirectional | General-purpose I/O on VDDANA; EXTINT[7], ADC AIN[7], AC AIN[3], PTC Y[5], SERCOM0/PAD[3], TCC1/WO[1]; driven low during internal startup. |
| 13 | VDDIO | power_in | Digital I/O supply, 1.8V to 3.6V, with 100nF and 10µF decoupling. |
| 14 | GND | power_in | Digital ground. |
| 15 | PA08 | bidirectional | General-purpose I/O on VDDIO (I2C capable); NMI, ADC AIN[16], PTC X[0], SERCOM0/PAD[0], SERCOM2/PAD[0], TCC0/WO[0], FECTRL[0]. |
| 16 | PA09 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[9], ADC AIN[17], PTC X[1], SERCOM0/PAD[1], SERCOM2/PAD[1], TCC0/WO[1], FECTRL[1]. |
| 17 | GNDANA | power_in | Ground for the analog power domain. |
| 18 | RFP | bidirectional | Positive pin of the differential antenna port (TX and RX), designed for 100Ω differential load; no DC path to ground or supply allowed. |
| 19 | RFN | bidirectional | Negative pin of the differential antenna port (TX and RX), designed for 100Ω differential load; no DC path to ground or supply allowed. |
| 20 | GNDANA | power_in | Ground for the analog power domain. |
| 21 | PA12 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[12], SERCOM2/PAD[0], TCC2/WO[0], FECTRL[2], AC/CMP[0]. |
| 22 | PA13 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[13], SERCOM2/PAD[1], TCC2/WO[1], FECTRL[3], AC/CMP[1]. |
| 23 | PA14 | bidirectional | General-purpose I/O on VDDIO; XIN crystal oscillator input, EXTINT[14], SERCOM2/PAD[2], TC3/WO[0], FECTRL[4], GCLK_IO[0]. |
| 24 | PA15 | bidirectional | General-purpose I/O on VDDIO; XOUT crystal oscillator output, EXTINT[15], SERCOM2/PAD[3], TC3/WO[1], FECTRL[5], GCLK_IO[1]. |
| 25 | PA16 | bidirectional | General-purpose I/O on VDDIO (I2C capable); PTC X[4], SERCOM1/PAD[0], SERCOM3/PAD[0], TCC2/WO[0], TCC0/WO[0], GCLK_IO[2]. |
| 26 | PA17 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[1], PTC X[5], SERCOM1/PAD[1], SERCOM3/PAD[1], TCC2/WO[1], TCC0/WO[1], GCLK_IO[3]. |
| 27 | PA18 | bidirectional | General-purpose I/O on VDDIO; EXTINT[2], PTC X[6], SERCOM1/PAD[2], SERCOM3/PAD[2], TC3/WO[0], TCC0/WO[2], AC/CMP[0]. |
| 28 | PA19 | bidirectional | General-purpose I/O on VDDIO; EXTINT[3], PTC X[7], SERCOM1/PAD[3], SERCOM3/PAD[3], TC3/WO[1], TCC0/WO[3], AC/CMP[1]. |
| 29 | GND | power_in | Digital ground. |
| 30 | DVDD | power_out | Output of the internal digital 1.8V radio voltage regulator; requires 100nF bypass capacitor. |
| 31 | PA22 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[6], PTC X[10], SERCOM3/PAD[0], SERCOM5/PAD[0], TC4/WO[0], TCC0/WO[4], GCLK_IO[6]. |
| 32 | PA23 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[7], PTC X[11], SERCOM3/PAD[1], SERCOM5/PAD[1], TC4/WO[1], TCC0/WO[5], USB SOF 1kHz, GCLK_IO[7]. |
| 33 | PA24 | bidirectional | General-purpose I/O on VDDIO; EXTINT[12], SERCOM3/PAD[2], SERCOM5/PAD[2], TC5/WO[0], TCC1/WO[2], USB_DM. |
| 34 | PA25 | bidirectional | General-purpose I/O on VDDIO; EXTINT[13], SERCOM3/PAD[3], SERCOM5/PAD[3], TC5/WO[1], TCC1/WO[3], USB_DP. |
| 35 | GND | power_in | Digital ground. |
| 36 | VDDIO | power_in | Digital I/O supply, 1.8V to 3.6V, with 100nF and 10µF decoupling. |
| 37 | PB22 | bidirectional | General-purpose I/O on VDDIO; EXTINT[6], SERCOM5/PAD[2], GCLK_IO[0]. |
| 38 | PB23 | bidirectional | General-purpose I/O on VDDIO; EXTINT[7], SERCOM5/PAD[3], GCLK_IO[1]. |
| 39 | PA27 | bidirectional | General-purpose I/O on VDDIO; EXTINT[15], SERCOM3/PAD[0], GCLK_IO[0]. |
| 40 | RESET | input | External reset, active low, with internal pull-up; low level threshold below 0.33VDDIO (VDDIO 1.8-2.0V) or 0.36VDDIO (2.7-3.6V). |
| 41 | PA28 | bidirectional | General-purpose I/O on VDDIO; EXTINT[8], SERCOM3/PAD[1], GCLK_IO[0]. |
| 42 | GND | power_in | Digital ground (name not printed in pinout figure; inferred). |
| 43 | VDDCORE | power_out | Internal regulator output for the core supply; requires decoupling capacitor. |
| 44 | VDDIN | power_in | Digital supply input, 1.8V to 3.6V, to the internal voltage regulator. |
| 45 | PA30 | bidirectional | General-purpose I/O on VDDIO; SWCLK serial wire clock (pull-up 1kΩ recommended), EXTINT[10], SERCOM1/PAD[2], TCC1/WO[0], GCLK_IO[0]. |
| 46 | PA31 | bidirectional | General-purpose I/O on VDDIO; SWDIO serial wire bidirectional data (active when debugger present), EXTINT[11], SERCOM1/PAD[3], TCC1/WO[1]. |
| 47 | PB02 | bidirectional | General-purpose I/O on VDDANA; EXTINT[2], ADC AIN[10], PTC Y[8], SERCOM5/PAD[0]. |
| 48 | PB03 | bidirectional | General-purpose I/O on VDDANA; EXTINT[3], ADC AIN[11], PTC Y[9], SERCOM5/PAD[1]. |
| 49 | EP | power_in | Exposed paddle, internally connected to GND; solder to digital ground for mechanical stability, not a replacement for the regular GND pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDDIO, VDDIN, VDDANA) | VDD | 1.8 | 3.6 | V | The same voltage must be applied to VDDIN, VDDIO and VDDANA | 20 | |
| VDDCORE internal regulated voltage | VDDCORE | 1.2 | V | Internal regulated output | 20 | ||
| Operating temperature (grade U) | -40 | 85 | °C | Package grade U, matte Sn plating | 6 | ||
| Maximum CPU frequency | Fmax | 48 | MHz | Cortex-M0+ maximum operating frequency | 1 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. | 871 |
CAD (KiCad official)
- Symbol:
ATSAMR21G18A-MU - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
atsamr21g18a-mu-etched.step/atsamr21g18a-mu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atsamr21g18a-mu.step/atsamr21g18a-mu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (1200 pp, sha256
1343e1031f25f537, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATSAMR21G18A-MU
**Microchip Tech** · MICROCHIP · QFN-48-EP(7x7)
ATSAMR21G18A-MU from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA00 | bidirectional | General-purpose I/O on VDDANA supply; XIN32 32kHz crystal input, EXTINT none, SERCOM1/PAD[0], TCC2/WO[0]. |
| 2 | PA01 | bidirectional | General-purpose I/O on VDDANA supply; XOUT32 32kHz crystal output, EXTINT[1], SERCOM1/PAD[1], TCC2/WO[1]. |
| 3 | XTAL2 | output | Output of the AT86RF233 16MHz reference crystal oscillator amplifier (XOSCRF); DC level 0.9V. |
| 4 | XTAL1 | input | Input of the 16MHz reference crystal oscillator amplifier (XOSCRF), also the input for an external clock reference; DC level 0.9V. |
| 5 | GNDANA | power_in | Ground for the analog power domain. |
| 6 | VDDANA | power_in | Analog supply, 1.8V to 3.6V, with 100nF and 10µF decoupling (optionally via ferrite bead). |
| 7 | AVDD | power_out | Output of the internal analog 1.8V voltage regulator for the radio; requires 100nF bypass capacitor. |
| 8 | GNDANA | power_in | Ground for the analog power domain. |
| 9 | PA04 | bidirectional | General-purpose I/O on VDDANA; EXTINT[4], ADC VREFB/AIN[4], AC AIN[0], PTC Y[2], SERCOM0/PAD[0], TCC0/WO[0]. |
| 10 | PA05 | bidirectional | General-purpose I/O on VDDANA; EXTINT[5], ADC AIN[5], AC AIN[1], PTC Y[3], SERCOM0/PAD[1], TCC0/WO[1]. |
| 11 | PA06 | bidirectional | General-purpose I/O on VDDANA; EXTINT[6], ADC AIN[6], AC AIN[2], PTC Y[4], SERCOM0/PAD[2], TCC1/WO[0]. |
| 12 | PA07 | bidirectional | General-purpose I/O on VDDANA; EXTINT[7], ADC AIN[7], AC AIN[3], PTC Y[5], SERCOM0/PAD[3], TCC1/WO[1]; driven low during internal startup. |
| 13 | VDDIO | power_in | Digital I/O supply, 1.8V to 3.6V, with 100nF and 10µF decoupling. |
| 14 | GND | power_in | Digital ground. |
| 15 | PA08 | bidirectional | General-purpose I/O on VDDIO (I2C capable); NMI, ADC AIN[16], PTC X[0], SERCOM0/PAD[0], SERCOM2/PAD[0], TCC0/WO[0], FECTRL[0]. |
| 16 | PA09 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[9], ADC AIN[17], PTC X[1], SERCOM0/PAD[1], SERCOM2/PAD[1], TCC0/WO[1], FECTRL[1]. |
| 17 | GNDANA | power_in | Ground for the analog power domain. |
| 18 | RFP | bidirectional | Positive pin of the differential antenna port (TX and RX), designed for 100Ω differential load; no DC path to ground or supply allowed. |
| 19 | RFN | bidirectional | Negative pin of the differential antenna port (TX and RX), designed for 100Ω differential load; no DC path to ground or supply allowed. |
| 20 | GNDANA | power_in | Ground for the analog power domain. |
| 21 | PA12 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[12], SERCOM2/PAD[0], TCC2/WO[0], FECTRL[2], AC/CMP[0]. |
| 22 | PA13 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[13], SERCOM2/PAD[1], TCC2/WO[1], FECTRL[3], AC/CMP[1]. |
| 23 | PA14 | bidirectional | General-purpose I/O on VDDIO; XIN crystal oscillator input, EXTINT[14], SERCOM2/PAD[2], TC3/WO[0], FECTRL[4], GCLK_IO[0]. |
| 24 | PA15 | bidirectional | General-purpose I/O on VDDIO; XOUT crystal oscillator output, EXTINT[15], SERCOM2/PAD[3], TC3/WO[1], FECTRL[5], GCLK_IO[1]. |
| 25 | PA16 | bidirectional | General-purpose I/O on VDDIO (I2C capable); PTC X[4], SERCOM1/PAD[0], SERCOM3/PAD[0], TCC2/WO[0], TCC0/WO[0], GCLK_IO[2]. |
| 26 | PA17 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[1], PTC X[5], SERCOM1/PAD[1], SERCOM3/PAD[1], TCC2/WO[1], TCC0/WO[1], GCLK_IO[3]. |
| 27 | PA18 | bidirectional | General-purpose I/O on VDDIO; EXTINT[2], PTC X[6], SERCOM1/PAD[2], SERCOM3/PAD[2], TC3/WO[0], TCC0/WO[2], AC/CMP[0]. |
| 28 | PA19 | bidirectional | General-purpose I/O on VDDIO; EXTINT[3], PTC X[7], SERCOM1/PAD[3], SERCOM3/PAD[3], TC3/WO[1], TCC0/WO[3], AC/CMP[1]. |
| 29 | GND | power_in | Digital ground. |
| 30 | DVDD | power_out | Output of the internal digital 1.8V radio voltage regulator; requires 100nF bypass capacitor. |
| 31 | PA22 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[6], PTC X[10], SERCOM3/PAD[0], SERCOM5/PAD[0], TC4/WO[0], TCC0/WO[4], GCLK_IO[6]. |
| 32 | PA23 | bidirectional | General-purpose I/O on VDDIO (I2C capable); EXTINT[7], PTC X[11], SERCOM3/PAD[1], SERCOM5/PAD[1], TC4/WO[1], TCC0/WO[5], USB SOF 1kHz, GCLK_IO[7]. |
| 33 | PA24 | bidirectional | General-purpose I/O on VDDIO; EXTINT[12], SERCOM3/PAD[2], SERCOM5/PAD[2], TC5/WO[0], TCC1/WO[2], USB_DM. |
| 34 | PA25 | bidirectional | General-purpose I/O on VDDIO; EXTINT[13], SERCOM3/PAD[3], SERCOM5/PAD[3], TC5/WO[1], TCC1/WO[3], USB_DP. |
| 35 | GND | power_in | Digital ground. |
| 36 | VDDIO | power_in | Digital I/O supply, 1.8V to 3.6V, with 100nF and 10µF decoupling. |
| 37 | PB22 | bidirectional | General-purpose I/O on VDDIO; EXTINT[6], SERCOM5/PAD[2], GCLK_IO[0]. |
| 38 | PB23 | bidirectional | General-purpose I/O on VDDIO; EXTINT[7], SERCOM5/PAD[3], GCLK_IO[1]. |
| 39 | PA27 | bidirectional | General-purpose I/O on VDDIO; EXTINT[15], SERCOM3/PAD[0], GCLK_IO[0]. |
| 40 | RESET | input | External reset, active low, with internal pull-up; low level threshold below 0.33*VDDIO (VDDIO 1.8-2.0V) or 0.36*VDDIO (2.7-3.6V). |
| 41 | PA28 | bidirectional | General-purpose I/O on VDDIO; EXTINT[8], SERCOM3/PAD[1], GCLK_IO[0]. |
| 42 | GND | power_in | Digital ground (name not printed in pinout figure; inferred). |
| 43 | VDDCORE | power_out | Internal regulator output for the core supply; requires decoupling capacitor. |
| 44 | VDDIN | power_in | Digital supply input, 1.8V to 3.6V, to the internal voltage regulator. |
| 45 | PA30 | bidirectional | General-purpose I/O on VDDIO; SWCLK serial wire clock (pull-up 1kΩ recommended), EXTINT[10], SERCOM1/PAD[2], TCC1/WO[0], GCLK_IO[0]. |
| 46 | PA31 | bidirectional | General-purpose I/O on VDDIO; SWDIO serial wire bidirectional data (active when debugger present), EXTINT[11], SERCOM1/PAD[3], TCC1/WO[1]. |
| 47 | PB02 | bidirectional | General-purpose I/O on VDDANA; EXTINT[2], ADC AIN[10], PTC Y[8], SERCOM5/PAD[0]. |
| 48 | PB03 | bidirectional | General-purpose I/O on VDDANA; EXTINT[3], ADC AIN[11], PTC Y[9], SERCOM5/PAD[1]. |
| 49 | EP | power_in | Exposed paddle, internally connected to GND; solder to digital ground for mechanical stability, not a replacement for the regular GND pins. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDDIO, VDDIN, VDDANA) | VDD | 1.8 | | 3.6 | V | The same voltage must be applied to VDDIN, VDDIO and VDDANA | 20 |
| VDDCORE internal regulated voltage | VDDCORE | | 1.2 | | V | Internal regulated output | 20 |
| Operating temperature (grade U) | | -40 | | 85 | °C | Package grade U, matte Sn plating | 6 |
| Maximum CPU frequency | Fmax | | | 48 | MHz | Cortex-M0+ maximum operating frequency | 1 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. | 871 |
## CAD (KiCad official)
- Symbol: `ATSAMR21G18A-MU`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `atsamr21g18a-mu-etched.step` / `atsamr21g18a-mu-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atsamr21g18a-mu.step` / `atsamr21g18a-mu.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/atsamr21g18a-mu-datasheet.pdf) (1200 pp, sha256 `1343e1031f25f537`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/atsamr21g18a-mu-datasheet.pdf)