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ATSAML10D15A-MUT
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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownATSAML10D15A-MUT
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-24-EP(4x4)
ATSAML10D15A-MUT from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA31/SWDIO | bidirectional | SWDIO serial-wire debug data pin and high-sink GPIO PA31 in the VDDIO domain, with alternates EXTINT[7], XY[19], SERCOM1/PAD[3], TC1/WO[1] and CCL OUT[1]; resets to Hi-Z I/O. |
| 2 | PA00/XIN32 | bidirectional | GPIO PA00 in the VDDANA domain that doubles as the 32.768 kHz crystal oscillator input XIN32, with alternates EXTINT[0], XY[0], OA1NEG, SERCOM1/PAD[0] and TC2/WO[0]; resets to Hi-Z I/O. |
| 3 | PA01/XOUT32 | bidirectional | GPIO PA01 in the VDDANA domain that doubles as the 32.768 kHz crystal oscillator output XOUT32, with alternates EXTINT[1], XY[1], OA1POS, SERCOM1/PAD[1] and TC2/WO[1]; resets to Hi-Z I/O. |
| 4 | PA02 | bidirectional | GPIO PA02 in the VDDANA domain with alternates AIN[0], XY[2], VOUT (DAC), OA0NEG, EXTINT[2] and SERCOM0/PAD[2]; its transition time must exceed 50 µs to avoid affecting XOSC32 cycle-to-cycle jitter. |
| 5 | PA03 | bidirectional | GPIO PA03 in the VDDANA domain with alternates VREFA, AIN[1], XY[3], OA2NEG, EXTINT[3] and SERCOM0/PAD[3]; its transition time must exceed 50 µs to avoid affecting XOSC32 cycle-to-cycle jitter. |
| 6 | PA04 | bidirectional | GPIO PA04 in the VDDANA domain with alternates VREFB, AIN[2], AIN[0] (comparator), OA2OUT, EXTINT[4], SERCOM0/PAD[0], TC0/WO[0] and CCL IN[0]; resets to Hi-Z I/O. |
| 7 | PA05 | bidirectional | GPIO PA05 in the VDDANA domain with alternates AIN[3], AIN[1] (comparator), XY[4], OA2POS, EXTINT[5], SERCOM0/PAD[1], TC0/WO[1] and CCL IN[1]; resets to Hi-Z I/O. |
| 8 | VDDANA | power_in | Analog supply voltage, 1.62 V to 3.63 V, which must be the same voltage applied to VDDIO; decouple with 100 nF and 10 µF close to the device. |
| 9 | GNDANA | power_in | Ground for the analog power domain. |
| 10 | PA08 | bidirectional | GPIO PA08 in the VDDIO domain with alternates NMI, AIN[6], XY[6], SERCOM1/PAD[0], SERCOM2/PAD[0], RTC/IN[0] and CCL IN[3]; resets to Hi-Z I/O. |
| 11 | PA14/XOSC | bidirectional | GPIO PA14 in the VDDIO domain that doubles as the crystal oscillator input XIN, with alternates EXTINT[3], XY[10], SERCOM2/PAD[2], SERCOM0/PAD[2], TC0/WO[0] and GCLK_IO[0]; resets to Hi-Z I/O. |
| 12 | PA15/XOUT | bidirectional | GPIO PA15 in the VDDIO domain that doubles as the crystal oscillator output XOUT, with alternates EXTINT[4], XY[11], SERCOM2/PAD[3], SERCOM0/PAD[3], TC0/WO[1] and GCLK_IO[1]; resets to Hi-Z I/O. |
| 13 | PA16 | bidirectional | High-sink GPIO PA16 in the VDDIO domain with alternates EXTINT[5], XY[12], SERCOM1/PAD[0], SERCOM0/PAD[0], RTC/IN[2], GCLK_IO[2] and CCL IN[0]; high-sink pins have different properties than standard pins. |
| 14 | PA17 | bidirectional | High-sink GPIO PA17 in the VDDIO domain with alternates EXTINT[6], XY[13], SERCOM1/PAD[1], SERCOM0/PAD[1], RTC/IN[3], GCLK_IO[3] and CCL IN[1]; high-sink pins have different properties than standard pins. |
| 15 | PA18 | bidirectional | GPIO PA18 in the VDDIO domain with alternates EXTINT[7], XY[14], SERCOM1/PAD[2], SERCOM0/PAD[2], TC2/WO[0], RTC/OUT[0], AC/CMP[0] and CCL IN[2]; resets to Hi-Z I/O. |
| 16 | PA19 | bidirectional | GPIO PA19 in the VDDIO domain with alternates EXTINT[0], XY[15], SERCOM1/PAD[3], SERCOM0/PAD[3], TC2/WO[1], RTC/OUT[1], AC/CMP[1] and CCL OUT[0]; resets to Hi-Z I/O. |
| 17 | PA22 | bidirectional | High-sink GPIO PA22 in the VDDIO domain with alternates EXTINT[1], XY[16], SERCOM0/PAD[0], SERCOM2/PAD[0], TC0/WO[0], RTC/OUT[2] and GCLK_IO[2]; high-sink pins have different properties than standard pins. |
| 18 | PA23 | bidirectional | High-sink GPIO PA23 in the VDDIO domain with alternates EXTINT[2], XY[17], SERCOM0/PAD[1], SERCOM2/PAD[1], TC0/WO[1], RTC/OUT[3] and GCLK_IO[1]; high-sink pins have different properties than standard pins. |
| 19 | RESET | input | External reset input in the VDDIO domain with an internal pull-up resistor, so an external pull-up is optional. |
| 20 | VDDCORE | power_out | Core supply voltage pin, 0.9 V to 1.2 V typical: in linear regulator mode it is the core output and external decoupling pin (1 µF and 100 nF), while in switched regulator mode it is the core input connected to VDDOUT through an inductor. |
| 21 | GND | power_in | Ground for the device; the exposed pad of the QFN package must also be connected to GND. |
| 22 | VDDOUT | power_out | On-chip switching-mode regulator output, connected to VDDCORE through a 10 µH inductor in switched regulator mode; not connected in linear regulator mode. |
| 23 | VDDIO | power_in | Digital supply voltage, 1.62 V to 3.63 V, which must be the same voltage applied to VDDANA; decouple with 100 nF and 10 µF close to the device and a 10 µH inductor for power filtering. |
| 24 | PA30/SWCLK | bidirectional | Serial-wire debug clock pin SWCLK in the VDDIO domain, which defaults to the SWCLK function with an internal pull-up and is also GPIO PA30 with alternates EXTINT[6], XY[18], SERCOM1/PAD[2], TC1/WO[0], GCLK_IO[0] and CCL IN[3]; a pull-up on SWCLK is recommended for reliable operation. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-24-EP(4x4) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, common VDD for VDDIO and VDDANA (nominal range) | VDD | 1.62 | 3.3 | 3.63 | V | Voltage range, nominal; same source must feed VDDIO and VDDANA | 24 |
| Core supply voltage range (VDDCORE) | VDDCORE | 0.9 | 1.2 | V | Voltage range; core, embedded memories, peripherals, FDPLL96M and DFLLULP | 24 | |
| Operating temperature, ordering suffix U | -40 | 85 | °C | Ordering suffix U = -40 - +85°C Matte Sn plating (this MPN) | 16 | ||
| Maximum CPU operating frequency | Fmax | 32 | MHz | Operating range DC to 32 MHz | 1 | ||
| External crystal oscillator frequency (XOSC) | 0.4 | 32 | MHz | External crystal between XIN and XOUT | 246 | ||
| Active mode current | 25 | μA/MHz | Active mode, as stated in Features list | 1 | |||
| Idle mode current | 10 | μA/MHz | Idle mode, as stated in Features list (1.5 μs wake-up time) | 1 | |||
| Off mode current | 100 | nA | Off sleep mode, as stated in Features list | 1 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. | 976 |
CAD (KiCad official)
- Symbol:
ATSAML10D15A-MUT - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
atsaml10d15a-mut-etched.step/atsaml10d15a-mut-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atsaml10d15a-mut.step/atsaml10d15a-mut.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (1127 pp, sha256
ee9c04451141173b, retrieved 2026-10-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).