component

ATSAMG55J19A-MU

Public Made by Adom

by adom

Microchip Tech Pre-ordered MCUs, QFN-64-EP(7.5x7.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatsamg55j19a-mufactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers atsamg55j19a-mu: viewers · Ray 7d ago
atsamg55j19a-mu-etched.glb Publish 0.1.0 · Ray 7d ago
atsamg55j19a-mu-etched.step atsamg55j19a-mu: factory component page (tier=mfr) · Ray 7d ago
atsamg55j19a-mu-hero.glb atsamg55j19a-mu: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
atsamg55j19a-mu-hero.overlay.json Publish 0.1.0 · Ray 7d ago
atsamg55j19a-mu.glb Publish 0.1.0 · Ray 7d ago
atsamg55j19a-mu.kicad_mod Publish 0.1.0 · Ray 7d ago
atsamg55j19a-mu.kicad_sym Publish 0.1.0 · Ray 7d ago
atsamg55j19a-mu.lbr Publish 0.1.0 · Ray 7d ago
atsamg55j19a-mu.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

ATSAMG55J19A-MU

Microchip Tech · Pre-ordered MCUs · QFN-64-EP(7.5x7.5)

ATSAMG55J19A-MU from Microchip Tech, in a QFN-64-EP(7.5x7.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDIO power_in Powers the peripheral I/O lines, RTC, RTT, SUPC, voltage regulator and ADC over 1.62V to 3.6V.
2 NRST bidirectional Bidirectional active-low reset with an integrated pull-up of about 100 kΩ to VDDIO, configured as an input by default.
3 PB12 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
4 PA4 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
5 PA3 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
6 PA0 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
7 PA1 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
8 PA5 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
9 VDDCORE power_in Powers the core, processor, embedded memories and peripherals except RTC, RTT and SUPC; it is recommended to connect it to VDDOUT.
10 TEST input TST pin selects the operating mode at powerup: low for normal operation and high for test mode, with a permanent pull-down of about 15 kΩ.
11 PA7 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
12 PA8 bidirectional Multiplexed PIO line; in peripheral function B it is the ADC external trigger input ADTRG.
13 GND power_in Ground pin, common to VDDCORE and VDDIO.
14 PB15 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
15 PB14 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
16 PA31 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
17 PA6 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
18 PA16 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
19 PA30 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
20 PA29 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
21 PA28 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
22 PA15 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
23 PA23 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
24 PA22 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
25 PA21 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
26 VDDUSB power_in Powers the USB on 64-pin packages over 3.0V to 3.6V.
27 VDDIO power_in Powers the peripheral I/O lines, RTC, RTT, SUPC, voltage regulator and ADC over 1.62V to 3.6V.
28 ADVREF input ADC analog reference on 64-pin packages; connect to VDDIO or let it rise with VDDIO at powerup to avoid overcurrent.
29 GND power_in Ground pin, common to VDDCORE and VDDIO.
30 VDDOUT power_out Voltage regulator output, which the datasheet recommends connecting to VDDCORE.
31 VDDIO power_in Powers the peripheral I/O lines, RTC, RTT, SUPC, voltage regulator and ADC over 1.62V to 3.6V.
32 VDDIO power_in Powers the peripheral I/O lines, RTC, RTT, SUPC, voltage regulator and ADC over 1.62V to 3.6V.
33 PA17 bidirectional Multiplexed PIO line; ADC analog input AD0 in the ADC mapping.
34 PA18 bidirectional Multiplexed PIO line; ADC analog input AD1 in the ADC mapping.
35 PA19 bidirectional Multiplexed PIO line; ADC analog input AD2 in the ADC mapping.
36 PA20 bidirectional Multiplexed PIO line; ADC analog input AD3 in the ADC mapping.
37 PB0 bidirectional Multiplexed PIO line; ADC analog input AD4 in the ADC mapping.
38 PB1 bidirectional Multiplexed PIO line; ADC analog input AD5 in the ADC mapping.
39 PB2 bidirectional Multiplexed PIO line; ADC analog input AD6 with wakeup WKUP12 in the ADC mapping.
40 PB3 bidirectional Multiplexed PIO line; ADC analog input AD7 with wakeup WKUP13 in the ADC mapping.
41 PA14 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
42 PA13 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
43 PA12 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
44 PA11 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
45 VDDCORE power_in Powers the core, processor, embedded memories and peripherals except RTC, RTT and SUPC; it is recommended to connect it to VDDOUT.
46 PB10 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
47 PB11 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
48 PA10 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
49 PA9 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
50 PB5 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
51 PA27 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
52 PA26 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
53 GND power_in Ground pin, common to VDDCORE and VDDIO.
54 PB6 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
55 PB7 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
56 PA25 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
57 PB13 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
58 PA24 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
59 PB8/XOUT bidirectional Multiplexed PIO line, shared with the XOUT oscillator output; its pull-up is disabled.
60 PB9/XIN bidirectional Multiplexed PIO line, shared with the XIN oscillator input; its pull-up is disabled.
61 PA2 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
62 PB4 bidirectional Multiplexed PIO line whose peripheral function is assigned by programming the PIO controller.
63 JTAGSEL input Selects the debug port when low (SW-DP or JTAG-DP) and boundary scan when high during powerup.
64 VDDIO power_in Powers the peripheral I/O lines, RTC, RTT, SUPC, voltage regulator and ADC over 1.62V to 3.6V.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(7.5x7.5)
Category Embedded Processors & Controllers
Pins 65

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC before performing the calculation, making the base address for the calculation word-aligned. ̶ Note: To generate the address of an instruction, the constant based on the value of the PC must be 114

CAD (KiCad official)

  • Symbol: ATSAMG55J19A-MU
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: QFN-64-EP(7.5x7.5) (KiCad packages3D, STEP)
  • 3D model files: atsamg55j19a-mu-etched.step / atsamg55j19a-mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsamg55j19a-mu.step / atsamg55j19a-mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1107 pp, sha256 3629fc41720dd133, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF