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ATSAME70Q21B-ANT

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleratsame70q21b-antfactory-2.0.0extractor-text

Verified ATSAME70Q21B-ANT

by Ray · last 31 Oct 2026 · 1 record · files match
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31 Oct 2026RayPublished by the parts factory: tier mfr, 144 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAME70Q21B-ANT · LQFP-144(20x20) · 144 pins
  • ✓copper: 144 copper pads, none touching another net
  • ✓datasheet: all 144 pin names found in the 1943-page datasheet
  • ✓distributor: lcsc C2054006, digikey ATSAME70Q21B-ANTTR-ND, mouser 556-ATSAME70Q21B-ANT
  • ✓family: LQFP-144_20x20mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ahxa9gpt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 144 pins = 144 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 144 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
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Contents

README

markdown

ATSAME70Q21B-ANT

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-144(20x20)

ATSAME70Q21B-ANT from Microchip Tech, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD0 bidirectional PIOD line 0 (VDDIO, reset I/PU/ST); DAC1 output, GTXCK, PWMC1_PWML0, SPI1_NPCS1, DCD0; also tied low for JTAG boundary scan.
2 PD31 bidirectional PIOD line 31 (VDDIO, reset I/PU/ST); QIO3, UTXD3, PCK2, ISI_D11.
3 VDDOUT power_out Voltage regulator output.
4 PE0 bidirectional PIOE line 0 (VDDIO, reset I/PU/ST); AFE1_AD11, D8, TIOA9, I2SC1_WS.
5 VDDIN power_in Voltage regulator input; also supplies ADC, DAC and analog comparator; must be at the same level as VDDIO.
6 PE1 bidirectional PIOE line 1 (VDDIO, reset I/PU/ST); D9, TIOB9, I2SC1_DO.
7 PE2 bidirectional PIOE line 2 (VDDIO, reset I/PU/ST); D10, TCLK9, I2SC1_DI.
8 VREFN power_in Negative analog reference (ground reference) for AFE and DAC.
9 VREFP power_in Positive analog reference voltage input for AFE and DAC; must rise simultaneously with VDDIO and VDDIN.
10 PE3 bidirectional PIOE line 3 (VDDIO, reset I/PU/ST); AFE1_AD10, D11, TIOA10.
11 PC0 bidirectional PIOC line 0 (VDDIO, reset I/PU/ST); AFE1_AD9, D0, PWMC0_PWML0.
12 PC27 bidirectional PIOC line 27 (VDDIO, reset I/PU/ST); AFE1_AD8, A9, TIOB4, SPI1_MOSI.
13 PC26 bidirectional PIOC line 26 (VDDIO, reset I/PU/ST); AFE1_AD7, A8, TIOA4, SPI1_MISO.
14 PC31 bidirectional PIOC line 31 (VDDIO, reset I/PU/ST); AFE1_AD6, A13, TCLK5.
15 PC30 bidirectional PIOC line 30 (VDDIO, reset I/PU/ST); AFE1_AD5, A12, TIOB5, SPI1_NPCS3.
16 PC29 bidirectional PIOC line 29 (VDDIO, reset I/PU/ST); AFE1_AD4, A11, TIOA5, SPI1_NPCS2.
17 PC12 bidirectional PIOC line 12 (VDDIO, reset I/PU/ST); AFE1_AD3, NCS3, TIOB8, CANRX1.
18 PC15 bidirectional PIOC line 15 (VDDIO, reset I/PU/ST); AFE1_AD2, NCS1/SDCS, PWMC0_PWML3.
19 PC13 bidirectional PIOC line 13 (VDDIO, reset I/PU/ST); AFE1_AD1, NWAIT, PWMC0_PWMH3.
20 PB1 bidirectional PIOB line 1 (VDDIO, reset I/PU/ST); AFE1_AD0/RTCOUT1, PWMC0_PWMH1, GTSUCOMP, TXD0, TK.
21 PB0 bidirectional PIOB line 0 (VDDIO, reset I/PU/ST); AFE0_AD10/RTCOUT0, PWMC0_PWMH0, RXD0, TF.
22 PA20 bidirectional PIOA line 20 (VDDIO, reset I/PU/ST); AFE0_AD9/WKUP10, PWMC0_PWML1, A16, I2SC1_CK.
23 PA19 bidirectional PIOA line 19 (VDDIO, reset I/PU/ST); AFE0_AD8/WKUP9, PWMC0_PWML0, A15, I2SC1_MCK.
24 PA18 bidirectional PIOA line 18 (VDDIO, reset I/PU/ST); AFE0_AD7, PWMC1_PWMEXTRG1, PCK2, A14.
25 PA17 bidirectional PIOA line 17 (VDDIO, reset I/PU/ST); AFE0_AD6, QIO2, PCK1, PWMC0_PWMH3.
26 PB2 bidirectional PIOB line 2 (VDDIO, reset I/PU/ST); AFE0_AD5, CANTX0, CTS0, SPI0_NPCS0.
27 PE4 bidirectional PIOE line 4 (VDDIO, reset I/PU/ST); AFE0_AD4, D12, TIOB10.
28 PE5 bidirectional PIOE line 5 (VDDIO, reset I/PU/ST); AFE0_AD3, D13, TCLK10.
29 VDDCORE power_in Core, embedded memories and peripherals supply; must not exceed VDDIN/VDDIO.
30 VDDIO power_in Peripheral I/O, backup and oscillator supply; must be 3.0-3.6 V for USB.
31 PB3 bidirectional PIOB line 3 (VDDIO, reset I/PU/ST); AFE0_AD2/WKUP12, CANRX0, PCK2, RTS0, ISI_D2.
32 PA21 bidirectional PIOA line 21 (VDDIO, reset I/PU/ST); AFE0_AD1/PIODCEN2, RXD1, PCK1, PWMC1_PWMFI0.
33 VDDCORE power_in Core, embedded memories and peripherals supply.
34 PD30 bidirectional PIOD line 30 (VDDIO, reset I/PU/ST); AFE0_AD0, UTXD3, ISI_D10.
35 PA7 bidirectional PIOA line 7 (VDDIO, reset PIO/HiZ); XIN32 32.768 kHz crystal input, PWMC0_PWMH3.
36 PA8 bidirectional PIOA line 8 (VDDIO, reset PIO/HiZ); XOUT32 32.768 kHz crystal output, PWMC1_PWMH3, AFE0_ADTRG.
37 PA22 bidirectional PIOA line 22 (VDDIO, reset I/PU/ST); PIODCCLK, RK, PWMC0_PWMEXTRG1, NCS2.
38 PC1 bidirectional PIOC line 1 (VDDIO, reset I/PU/ST); D1, PWMC0_PWML1.
39 PC2 bidirectional PIOC line 2 (VDDIO, reset I/PU/ST); D2, PWMC0_PWML2.
40 PC3 bidirectional PIOC line 3 (VDDIO, reset I/PU/ST); D3, PWMC0_PWML3.
41 PC4 bidirectional PIOC line 4 (VDDIO, reset I/PU/ST); D4.
42 PA13 bidirectional PIOA line 13 (VDDIO, reset I/PU/ST); PIODC7, QIO0, PWMC0_PWMH2, PWMC1_PWML1.
43 VDDIO power_in Peripheral I/O, backup and oscillator supply.
44 GND power_in Ground.
45 PA16 bidirectional PIOA line 16 (VDDIO, reset I/PU/ST); D15, TIOB1, PWMC0_PWML2, I2SC0_DI.
46 PA23 bidirectional PIOA line 23 (VDDIO, reset I/PU/ST); SCK1, PWMC0_PWMH0, A19, PWMC1_PWML2.
47 PD27 bidirectional PIOD line 27 (VDDIO, reset I/PU/ST); PWMC0_PWML3, SPI0_NPCS3, TWD2, ISI_D8.
48 PC7 bidirectional PIOC line 7 (VDDIO, reset I/PU/ST); D7, TCLK6.
49 PA15 bidirectional PIOA line 15 (VDDIO, reset I/PU/ST); D14, TIOA1, PWMC0_PWML3, I2SC0_WS.
50 VDDCORE power_in Core, embedded memories and peripherals supply.
51 PA14 bidirectional PIOA line 14 (VDDIO, reset I/PU/ST); WKUP8/PIODCEN1, QSCK, PWMC0_PWMH3, PWMC1_PWMH1.
52 PD25 bidirectional PIOD line 25 (VDDIO, reset I/PU/ST); PWMC0_PWML1, SPI0_NPCS1, URXD2, ISI_VSYNC.
53 PD26 bidirectional PIOD line 26 (VDDIO, reset I/PU/ST); PWMC0_PWML2, TD, UTXD2, UTXD1.
54 PC6 bidirectional PIOC line 6 (VDDIO, reset I/PU/ST); D6, TIOB6.
55 PD24 bidirectional PIOD line 24 (VDDIO, reset I/PU/ST); PWMC0_PWML0, RF, TCLK11, ISI_HSYNC.
56 PA24 bidirectional PIOA line 24 (VDDIO, reset I/PU/ST); RTS1, PWMC0_PWMH1, A20, ISI_PCK.
57 PD23 bidirectional PIOD line 23 (VDDIO, reset I/PU/ST); PWMC0_PWMH3.
58 PC5 bidirectional PIOC line 5 (VDDIO, reset I/PU/ST); D5, TIOA6.
59 PA25 bidirectional PIOA line 25 (VDDIO, reset I/PU/ST); CTS1, PWMC0_PWMH2, A23, MCCK.
60 PD22 bidirectional PIOD line 22 (VDDIO, reset I/PU/ST); PWMC0_PWMH2, SPI0_SPCK, TIOB11, ISI_D0.
61 GND power_in Ground.
62 PA26 bidirectional PIOA line 26 (VDDIO, reset I/PU/ST); DCD1, TIOA2, MCDA2, PWMC1_PWMFI1.
63 PD21 bidirectional PIOD line 21 (VDDIO, reset I/PU/ST); PWMC0_PWMH1, SPI0_MOSI, TIOA11, ISI_D1.
64 PA11 bidirectional PIOA line 11 (VDDIO, reset I/PU/ST); WKUP7/PIODC5, QCS, PWMC0_PWMH0, PWMC1_PWML0.
65 PD20 bidirectional PIOD line 20 (VDDIO, reset I/PU/ST); PWMC0_PWMH0, SPI0_MISO, GTSUCOMP.
66 PA10 bidirectional PIOA line 10 (VDDIO, reset I/PU/ST); PIODC4, UTXD0, PWMC0_PWMEXTRG0, RD.
67 PD19 bidirectional PIOD line 19 (VDDIO, reset I/PU/ST); NCS3, CTS2, UTXD4.
68 PA12 bidirectional PIOA line 12 (VDDIO, reset I/PU/ST); PIODC6, QIO1, PWMC0_PWMH1, PWMC1_PWMH0.
69 PD18 bidirectional PIOD line 18 (VDDIO, reset I/PU/ST); NCS1/SDCS, RTS2, URXD4.
70 PA27 bidirectional PIOA line 27 (VDDIO, reset I/PU/ST); DTR1, TIOB2, MCDA3, ISI_D7.
71 PD28 bidirectional PIOD line 28 (VDDIO, reset I/PU/ST); WKUP5, URXD3, TWCK2, ISI_D9.
72 VDDIO power_in Peripheral I/O, backup and oscillator supply.
73 PA5 bidirectional PIOA line 5 (VDDIO, reset I/PU/ST); WKUP4/PIODC2, PWMC1_PWML3, ISI_D4, URXD1.
74 PD17 bidirectional PIOD line 17 (VDDIO, reset I/PU/ST); GTXER, SCK2.
75 PA9 bidirectional PIOA line 9 (VDDIO, reset I/PU/ST); WKUP6/PIODC3, URXD0, ISI_D3, PWMC0_PWMFI0.
76 PC28 bidirectional PIOC line 28 (VDDIO, reset I/PU/ST); A10, TCLK4, SPI1_NPCS1.
77 PA4 bidirectional PIOA line 4 (VDDIO, reset I/PU/ST); WKUP3/PIODC1, TWCK0, TCLK0, UTXD1.
78 PD16 bidirectional PIOD line 16 (VDDIO, reset I/PU/ST); GTX3, TXD2.
79 PB6 bidirectional PIOB line 6 (VDDIO, reset PIO/I/ST); SWDIO/TMS debug pin, system I/O selectable via CCFG_SYSIO.
80 VDDIO power_in Peripheral I/O, backup and oscillator supply.
81 VDDCORE power_in Core, embedded memories and peripherals supply.
82 PC8 bidirectional PIOC line 8 (VDDIO, reset I/PU/ST); NWR0/NWE, TIOA7.
83 NRST bidirectional Microcontroller reset, active low, input/output with internal pull-up (VDDIO).
84 PD14 bidirectional PIOD line 14 (VDDIO, reset I/PU/ST); GRXCK.
85 TST input Test select input with internal pull-down (about 15 kΩ), used for JTAG boundary scan or fast flash programming; can be left unconnected.
86 PC9 bidirectional PIOC line 9 (VDDIO, reset I/PU/ST); NANDOE, TIOB7.
87 PB12 bidirectional PIOB line 12 (VDDIO, reset I/PD/ST); ERASE, PWMC0_PWML1, GTSUCOMP, PCK0; must be low at startup when not used for erase.
88 PD13 bidirectional PIOD line 13 (VDDIO, reset I/PU/ST); GCOL.
89 PB7 bidirectional PIOB line 7 (VDDIO, reset PIO/I/ST); SWCLK/TCK debug pin, system I/O selectable via CCFG_SYSIO.
90 PC10 bidirectional PIOC line 10 (VDDIO, reset I/PU/ST); NANDWE, TCLK7.
91 PA3 bidirectional PIOA line 3 (VDDIO, reset I/PU/ST); PIODC0, TWD0, LONCOL1, PCK2.
92 PD12 bidirectional PIOD line 12 (VDDIO, reset I/PU/ST); GRX3, CANTX1, SPI0_NPCS2, ISI_D6.
93 PA2 bidirectional PIOA line 2 (VDDIO, reset I/PU/ST); WKUP2, PWMC0_PWMH1, DATRG.
94 PC11 bidirectional PIOC line 11 (VDDIO, reset I/PU/ST); NRD, TIOA8.
95 GND power_in Ground.
96 VDDIO power_in Peripheral I/O, backup and oscillator supply.
97 PC14 bidirectional PIOC line 14 (VDDIO, reset I/PU/ST); NCS0, TCLK8, CANTX1.
98 PD11 bidirectional PIOD line 11 (VDDIO, reset I/PU/ST); GRX2, PWMC0_PWMH0, GTSUCOMP, ISI_D5.
99 PA1 bidirectional PIOA line 1 (VDDIO, reset I/PU/ST); WKUP1, PWMC0_PWML0, TIOB0, A18, I2SC0_CK.
100 PC16 bidirectional PIOC line 16 (VDDIO, reset I/PU/ST); A21/NANDALE.
101 PD10 bidirectional PIOD line 10 (VDDIO, reset I/PD/ST); GCRS, PWMC0_PWML0, TD, MLBSIG.
102 PA0 bidirectional PIOA line 0 (VDDIO, reset I/PU/ST); WKUP0, PWMC0_PWMH0, TIOA0, A17, I2SC0_MCK.
103 PC17 bidirectional PIOC line 17 (VDDIO, reset I/PU/ST); A22/NANDCLE.
104 JTAGSEL input JTAG selection input, active high, with internal pull-down (about 15 kΩ); high selects JTAG boundary scan, low selects SW-DP.
105 PB4 bidirectional PIOB line 4 (VDDIO, reset I/PU/ST); TDI, TWD1, PWMC0_PWMH2, MLBCLK, TXD1.
106 PD15 bidirectional PIOD line 15 (VDDIO, reset I/PU/ST); GTX2, RXD2, NWR1/NBS1.
107 VDDCORE power_in Core, embedded memories and peripherals supply.
108 PD29 bidirectional PIOD line 29 (VDDIO, reset I/PU/ST); general-purpose I/O with no peripheral function listed.
109 PB5 bidirectional PIOB line 5 (VDDIO, reset O/PU); TDO/TRACESWO/WKUP13, TWCK1, PWMC0_PWML0, MLBDAT, TD.
110 PD9 bidirectional PIOD line 9 (VDDIO, reset I/PU/ST); GMDIO, PWMC0_PWMFI2, AFE1_ADTRG.
111 PC18 bidirectional PIOC line 18 (VDDIO, reset I/PU/ST); A0/NBS0, PWMC0_PWML1.
112 PA28 bidirectional PIOA line 28 (VDDIO, reset I/PU/ST); DSR1, TCLK1, MCCDA, PWMC1_PWMFI2.
113 PD8 bidirectional PIOD line 8 (VDDIO, reset I/PU/ST); GMDC, PWMC0_PWMFI1, TRACECLK.
114 PA6 bidirectional PIOA line 6 (VDDIO, reset I/PU/ST); PCK0, UTXD1.
115 GND power_in Ground.
116 PA30 bidirectional PIOA line 30 (VDDIO, reset I/PU/ST); WKUP11, PWMC0_PWML2, PWMC1_PWMEXTRG0, MCDA0, I2SC0_DO.
117 PC19 bidirectional PIOC line 19 (VDDIO, reset I/PU/ST); A1, PWMC0_PWMH2.
118 PA31 bidirectional PIOA line 31 (VDDIO, reset I/PU/ST); SPI0_NPCS1, PCK2, MCDA1, PWMC1_PWMH2.
119 PD7 bidirectional PIOD line 7 (VDDIO, reset I/PU/ST); GRXER, PWMC1_PWMH3, TRACED3, RI2.
120 PC20 bidirectional PIOC line 20 (VDDIO, reset I/PU/ST); A2, PWMC0_PWML2.
121 PD6 bidirectional PIOD line 6 (VDDIO, reset I/PU/ST); GRX1, PWMC1_PWML3, TRACED2, DSR2.
122 PC21 bidirectional PIOC line 21 (VDDIO, reset I/PU/ST); A3, PWMC0_PWMH3.
123 VDDPLL power_in Supply for PLLA and the fast RC oscillator; noise sensitive.
124 PC22 bidirectional PIOC line 22 (VDDIO, reset I/PU/ST); A4, PWMC0_PWML3.
125 PD5 bidirectional PIOD line 5 (VDDIO, reset I/PU/ST); GRX0, PWMC1_PWMH2, TRACED1, DTR2.
126 PD4 bidirectional PIOD line 4 (VDDIO, reset I/PU/ST); GRXDV, PWMC1_PWML2, TRACED0, DCD2.
127 PC23 bidirectional PIOC line 23 (VDDIO, reset I/PU/ST); A5, TIOA3.
128 PD3 bidirectional PIOD line 3 (VDDIO, reset I/PU/ST); GTX1, PWMC1_PWMH1, UTXD4, RI0.
129 PA29 bidirectional PIOA line 29 (VDDIO, reset I/PU/ST); RI1, TCLK2.
130 PC24 bidirectional PIOC line 24 (VDDIO, reset I/PU/ST); A6, TIOB3, SPI1_SPCK.
131 PD2 bidirectional PIOD line 2 (VDDIO, reset I/PU/ST); GTX0, PWMC1_PWML1, SPI1_NPCS3, DSR0.
132 PD1 bidirectional PIOD line 1 (VDDIO, reset I/PU/ST); GTXEN, PWMC1_PWMH0, SPI1_NPCS2, DTR0.
133 PC25 bidirectional PIOC line 25 (VDDIO, reset I/PU/ST); A7, TCLK3, SPI1_NPCS0.
134 VDDUTMII power_in USB transceiver interface supply; must be connected to VDDIO (3.0-3.6 V for USB).
135 GND power_in Ground.
136 HSDM bidirectional USB high-speed data minus (D-).
137 HSDP bidirectional USB high-speed data plus (D+).
138 GND power_in Ground.
139 VDDUTMIC power_in USB transceiver core supply; must always be connected even when USB is unused.
140 VBG input Bandgap voltage pin (input), see schematic checklist for connection.
141 PB8 bidirectional PIOB line 8 (VDDIO, reset PIO/HiZ); XOUT main crystal oscillator output (3 to 20 MHz).
142 PB9 bidirectional PIOB line 9 (VDDIO, reset PIO/HiZ); XIN main crystal oscillator input (3 to 20 MHz).
143 VDDPLLUSB power_in Supply for UTMI PLL and 3 to 20 MHz oscillator; noise sensitive, 3.0-3.6 V for USB.
144 PB13 bidirectional PIOB line 13 (VDDIO, reset I/PU/ST); DAC0 output, PWMC0_PWML2, PCK0, SCK0.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-144(20x20)
Category Single Chip Microcomputer/Microcontroller
Pins 144

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (Industrial temperature devices) 1.7 3.6 V Single supply voltage, Industrial Temperature Devices 2
Operating temperature range (Industrial) -40 105 °C N = Industrial (-40 - +105°C) 15
VDDIO range for USB operation VDDIO 3 3.6 V For USB operations 43
Cortex-M7 maximum frequency fMAX 300 MHz Arm Cortex-M7 processor 16
Bus matrix maximum frequency fMAX 150 MHz 12-layer AHB bus matrix 16
Maximum VDDCORE/VDDPLL/VDDUTMIC voltage spread 0.6 V VDDCORE, VDDPLL and VDDUTMIC levels must not vary by more than 0.6V 43
VDDCORE falling slope 20 V/ms Powerdown, VDDCORE not supplied by embedded regulator; must not be faster than 20V/ms 44
Backup mode current 1.1 μA Backup mode with RTC, RTT and wakeup logic enabled 1
Wakeup time from Wait mode 10 μs Wait mode, time until first instruction fetched, PLL startup excluded 45
I/O pull-up/pull-down resistance 100 kΩ Typical value for all I/Os 48
JTAGSEL pulldown resistance 15 kΩ about 15 kΩ to GND 49
NRST pull-up resistance 100 kΩ to VDDIO, about 100 kΩ 50
ERASE pull-down resistance 100 kΩ to GND, about 100 kΩ 50

CAD (KiCad official)

  • Symbol: ATSAME70Q21B-ANT
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: atsame70q21b-ant-etched.step / atsame70q21b-ant-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsame70q21b-ant.step / atsame70q21b-ant.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1943 pp, sha256 94ed9d6997caca1c, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF