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ATSAME70N21B-ANT

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified ATSAME70N21B-ANT

by Ray · last 30 Oct 2026 · 1 record · files match
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30 Oct 2026RayPublished by the parts factory: tier mfr, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAME70N21B-ANT · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 1943-page datasheet
  • ✓distributor: lcsc C2053868, digikey ATSAME70N21B-ANTTR-ND, mouser 556-ATSAME70N21B-ANT
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-j6ntikrc/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
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ATSAME70N21B-ANT

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

ATSAME70N21B-ANT from Microchip Tech, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD0 bidirectional PIO line PD0, reset PIO input with pull-up and Schmitt trigger; alternates are DAC1 (analog output, footnote 11), A GTXCK, B PWMC1_PWML0, C SPI1_NPCS1, D DCD0.
2 PD31 bidirectional PIO line PD31, reset PIO input with pull-up and Schmitt trigger; peripheral A QIO3, B UTXD3, C PCK2, D ISI_D11.
3 GND power_in Ground pin for the voltage regulator, core, chip and peripheral I/O lines.
4 VDDOUT power_out Embedded voltage regulator output pin.
5 VDDIN power_in Voltage regulator input; also supplies the AFE/ADC, DAC and analog voltage comparator.
6 VREFN power_in AFE reference voltage VREFN, on the GND power rail.
7 GND power_in Ground pin.
8 GND power_in Ground pin.
9 VREFP power_in AFE and DAC voltage reference input; must rise simultaneously with VDDIO and VDDIN to prevent overcurrent at powerup.
10 GND power_in Ground pin.
11 PB1 bidirectional PIO line PB1, reset PIO input with pull-up and Schmitt trigger; alternates are AFE1_AD0/RTCOUT1 (analog input has priority over RTCOUT1), A PWMC0_PWMH1, B GTSUCOMP, C TXD0, D TK.
12 PB0 bidirectional PIO line PB0, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD10/RTCOUT0 (analog input has priority over RTCOUT0), A PWMC0_PWMH0, C RXD0, D TF.
13 PA20 bidirectional PIO line PA20, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD9/WKUP10 (analog input has priority over WKUP10), B PWMC0_PWML1, C A16, D I2SC1_CK.
14 PA19 bidirectional PIO line PA19, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD8/WKUP9 (analog input has priority over WKUP9), B PWMC0_PWML0, C A15, D I2SC1_MCK.
15 PA18 bidirectional PIO line PA18, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD7 (analog input, footnote 5), A PWMC1_PWMEXTRG1, B PCK2, C A14.
16 PA17 bidirectional PIO line PA17, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD6 (analog input, footnote 5), A QIO2, B PCK1, C PWMC0_PWMH3.
17 PB2 bidirectional PIO line PB2, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD5 (analog input, footnote 5), A CANTX0, C CTS0, D SPI0_NPCS0.
18 VDDCORE power_in Core supply for the core, embedded memories and peripherals.
19 VDDIO power_in Peripheral I/O supply for the I/O buffers, backup part, 1 Kbyte backup SRAM, 32 kHz crystal oscillator and oscillator pads.
20 PB3 bidirectional PIO line PB3, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD2/WKUP12 (analog input has priority over WKUP12), A CANRX0, B PCK2, C RTS0, D ISI_D2.
21 PA21 bidirectional PIO line PA21, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD1/PIODCEN2 (analog input has priority over PIODCEN2), A RXD1, B PCK1, C PWMC1_PWMFI0.
22 VDDCORE power_in Core supply for the core, embedded memories and peripherals.
23 PD30 bidirectional PIO line PD30, reset PIO input with pull-up and Schmitt trigger; alternates are AFE0_AD0 (analog input, footnote 5), A UTXD3, D ISI_D10.
24 PA7 bidirectional PIO line PA7, reset PIO with high-impedance; alternate XIN32 is the 32.768 kHz oscillator input (see Slow Clock Generator), B PWMC0_PWMH3.
25 PA8 bidirectional PIO line PA8, reset PIO with high-impedance; alternate XOUT32 is the 32.768 kHz oscillator output, A PWMC1_PWMH3, B AFE0_ADTRG.
26 PA22 bidirectional PIO line PA22, reset PIO input with pull-up and Schmitt trigger; alternate PIODCCLK (parallel capture clock), A RK, B PWMC0_PWMEXTRG1, C NCS2.
27 PA13 bidirectional PIO line PA13, reset PIO input with pull-up and Schmitt trigger; alternate PIODC7 (parallel capture data), A QIO0, B PWMC0_PWMH2, C PWMC1_PWML1.
28 VDDIO power_in Peripheral I/O supply for the I/O buffers, backup part, 1 Kbyte backup SRAM, 32 kHz crystal oscillator and oscillator pads.
29 GND power_in Ground pin.
30 PA16 bidirectional PIO line PA16, reset PIO input with pull-up and Schmitt trigger; A D15, B TIOB1, C PWMC0_PWML2, D I2SC0_DI.
31 PA23 bidirectional PIO line PA23, reset PIO input with pull-up and Schmitt trigger; A SCK1, B PWMC0_PWMH0, C A19, D PWMC1_PWML2.
32 PD27 bidirectional PIO line PD27, reset PIO input with pull-up and Schmitt trigger; A PWMC0_PWML3, B SPI0_NPCS3, C TWD2, D ISI_D8.
33 PA15 bidirectional PIO line PA15, reset PIO input with pull-up and Schmitt trigger; A D14, B TIOA1, C PWMC0_PWML3, D I2SC0_WS.
34 PA14 bidirectional PIO line PA14, reset PIO input with pull-up and Schmitt trigger; alternates are WKUP8/PIODCEN1 (PIODCEN1 has priority over WKUP8), A QSCK, B PWMC0_PWMH3, C PWMC1_PWMH1.
35 PD25 bidirectional PIO line PD25, reset PIO input with pull-up and Schmitt trigger; A PWMC0_PWML1, B SPI0_NPCS1, C URXD2, D ISI_VSYNC.
36 PD26 bidirectional PIO line PD26, reset PIO input with pull-up and Schmitt trigger; A PWMC0_PWML2, B TD, C UTXD2, D UTXD1.
37 PD24 bidirectional PIO line PD24, reset PIO input with pull-up and Schmitt trigger; A PWMC0_PWML0, B RF, C TCLK11, D ISI_HSYNC.
38 PA24 bidirectional PIO line PA24, reset PIO input with pull-up and Schmitt trigger; A RTS1, B PWMC0_PWMH1, C A20, D ISI_PCK.
39 VDDCORE power_in Core supply for the core, embedded memories and peripherals.
40 PA25 bidirectional PIO line PA25, reset PIO input with pull-up and Schmitt trigger; A CTS1, B PWMC0_PWMH2, C A23, D MCCK.
41 PD22 bidirectional PIO line PD22, reset PIO input with pull-up and Schmitt trigger; A PWMC0_PWMH2, B SPI0_SPCK, C TIOB11, D ISI_D0.
42 PA26 bidirectional PIO line PA26, reset PIO input with pull-up and Schmitt trigger; A DCD1, B TIOA2, C MCDA2, D PWMC1_PWMFI1.
43 PD21 bidirectional PIO line PD21, reset PIO input with pull-up and Schmitt trigger; A PWMC0_PWMH1, B SPI0_MOSI, C TIOA11, D ISI_D1.
44 PA11 bidirectional PIO line PA11, reset PIO input with pull-up and Schmitt trigger; alternates are WKUP7/PIODC5 (PIODC5 has priority over WKUP7), A QCS, B PWMC0_PWMH0, C PWMC1_PWML0.
45 PD20 bidirectional PIO line PD20, reset PIO input with pull-up and Schmitt trigger; A PWMC0_PWMH0, B SPI0_MISO, C GTSUCOMP.
46 PA10 bidirectional PIO line PA10, reset PIO input with pull-up and Schmitt trigger; alternate PIODC4 (parallel capture data), A UTXD0, B PWMC0_PWMEXTRG0, C RD.
47 PD19 bidirectional PIO line PD19, reset PIO input with pull-up and Schmitt trigger; A NCS3, B CTS2, C UTXD4.
48 PA12 bidirectional PIO line PA12, reset PIO input with pull-up and Schmitt trigger; alternate PIODC6 (parallel capture data), A QIO1, B PWMC0_PWMH1, C PWMC1_PWMH0.
49 PD18 bidirectional PIO line PD18, reset PIO input with pull-up and Schmitt trigger; A NCS1, B RTS2, C URXD4.
50 PA27 bidirectional PIO line PA27, reset PIO input with pull-up and Schmitt trigger; A DTR1, B TIOB2, C MCDA3, D ISI_D7 (direction not stated in the table).
51 PD28 bidirectional PIO line PD28, reset PIO input with pull-up and Schmitt trigger; alternate WKUP5 (wakeup input), A URXD3, B CANRX1, C TWCK2, D ISI_D9.
52 PA5 bidirectional PIO line PA5, reset PIO input with pull-up and Schmitt trigger; alternate WKUP4/PIODC2 (PIODC2 has priority over WKUP4), A PWMC1_PWML3, B ISI_D4, C URXD1.
53 PD17 bidirectional PIO line PD17, reset PIO input with pull-up and Schmitt trigger; A GTXER, B SCK2.
54 PA9 bidirectional PIO line PA9, reset PIO input with pull-up and Schmitt trigger; alternate WKUP6/PIODC3 (PIODC3 has priority over WKUP6), A URXD0, B ISI_D3, C PWMC0_PWMFI0.
55 PA4 bidirectional PIO line PA4, reset PIO input with pull-up and Schmitt trigger; alternate WKUP3/PIODC1 (PIODC1 has priority over WKUP3), A TWCK0, B TCLK0, C UTXD1.
56 PD16 bidirectional PIO line PD16, reset PIO input with pull-up and Schmitt trigger; A GTX3, B TXD2.
57 PB6 bidirectional PIO line PB6, reset PIO input with Schmitt trigger; alternate SWDIO/TMS (Serial Wire Debug data / JTAG mode select).
58 NRST input Microcontroller reset pin, active low, with pull-up in PIO state (Table 6-2 lists direction I).
59 PD14 bidirectional PIO line PD14, reset PIO input with pull-up and Schmitt trigger; A GRXCK.
60 TST input Test select input; integrates a permanent pull-down to GND and is used for JTAG boundary scan or Fast Flash Programming.
61 PB12 bidirectional PIO line PB12, reset PIO input with pull-down and Schmitt trigger; alternate ERASE (Flash erase mode), A PWMC0_PWML1, B GTSUCOMP, D PCK0.
62 PD13 bidirectional PIO line PD13, reset PIO input with pull-up and Schmitt trigger; A GCOL.
63 PB7 bidirectional PIO line PB7, reset PIO input with Schmitt trigger; alternate SWCLK/TCK (Serial Wire clock / JTAG test clock).
64 PA3 bidirectional PIO line PA3, reset PIO input with pull-up and Schmitt trigger; alternate PIODC0 (parallel capture data), A TWD0, B LONCOL1, C PCK2.
65 PD12 bidirectional PIO line PD12, reset PIO input with pull-up and Schmitt trigger; A GRX3, B CANTX1, C SPI0_NPCS2, D ISI_D6.
66 PA2 bidirectional PIO line PA2, reset PIO input with pull-up and Schmitt trigger; alternate WKUP2 (wakeup input), A PWMC0_PWMH1, C DATRG.
67 GND power_in Ground pin.
68 VDDIO power_in Peripheral I/O supply for the I/O buffers, backup part, 1 Kbyte backup SRAM, 32 kHz crystal oscillator and oscillator pads.
69 PD11 bidirectional PIO line PD11, reset PIO input with pull-up and Schmitt trigger; A GRX2, B PWMC0_PWMH0, C GTSUCOMP, D ISI_D5.
70 PA1 bidirectional PIO line PA1, reset PIO input with pull-up and Schmitt trigger; alternate WKUP1 (wakeup input), A PWMC0_PWML0, B TIOB0, C A18, D I2SC0_CK.
71 PD10 bidirectional PIO line PD10, reset PIO input with pull-down and Schmitt trigger; A GCRS, B PWMC0_PWML0, C TD, D MLBSIG.
72 PA0 bidirectional PIO line PA0, reset PIO input with pull-up and Schmitt trigger; alternate WKUP0 (wakeup input), A PWMC0_PWMH0, B TIOA0, C A17, D I2SC0_MCK.
73 JTAGSEL input JTAG selection input; high level selects JTAG boundary scan, and it integrates a permanent pull-down to GND.
74 PB4 bidirectional PIO line PB4, reset PIO input with pull-down and Schmitt trigger; alternate TDI (JTAG test data in), A TWD1, B PWMC0_PWMH2, C MLBCLK, D TXD1.
75 PD15 bidirectional PIO line PD15, reset PIO input with pull-up and Schmitt trigger; A GTX2, B RXD2, C NWR1/NBS1.
76 VDDCORE power_in Core supply for the core, embedded memories and peripherals.
77 PB5 bidirectional PIO line PB5, reset output with pull-up; alternate TDO/TRACESWO/WKUP13 (JTAG data out / trace output / wakeup input), A TWCK1, B PWMC0_PWML0, C MLBDAT, D TD.
78 PD9 bidirectional PIO line PD9, reset PIO input with pull-up and Schmitt trigger; A GMDIO, B PWMC0_PWMFI2, C AFE1_ADTRG.
79 PA28 bidirectional PIO line PA28, reset PIO input with pull-up and Schmitt trigger; A DSR1, B TCLK1, C MCCDA, D PWMC1_PWMFI2.
80 PD8 bidirectional PIO line PD8, reset PIO input with pull-up and Schmitt trigger; A GMDC, B PWMC0_PWMFI1, D TRACECLK.
81 VDDIO power_in Peripheral I/O supply for the I/O buffers, backup part, 1 Kbyte backup SRAM, 32 kHz crystal oscillator and oscillator pads.
82 PA30 bidirectional PIO line PA30, reset PIO input with pull-up and Schmitt trigger; alternate WKUP11 (wakeup input), A PWMC0_PWML2, B PWMC1_PWMEXTRG0, C MCDA0, D I2SC0_D0.
83 PA31 bidirectional PIO line PA31, reset PIO input with pull-up and Schmitt trigger; A SPI0_NPCS1, B PCK2, C MCDA1, D PWMC1_PWMH2.
84 PD7 bidirectional PIO line PD7, reset PIO input with pull-up and Schmitt trigger; A GRXER, B PWMC1_PWMH3, C TRACED3, D RI2.
85 PD6 bidirectional PIO line PD6, reset PIO input with pull-up and Schmitt trigger; A GRX1, B PWMC1_PWML3, C TRACED2, D DSR2.
86 VDDPLL power_in Supply for PLLA and the fast RC oscillator.
87 PD5 bidirectional PIO line PD5, reset PIO input with pull-up and Schmitt trigger; A GRX0, B PWMC1_PWMH2, C TRACED1, D DTR2.
88 PD4 bidirectional PIO line PD4, reset PIO input with pull-up and Schmitt trigger; A GRXDV, B PWMC1_PWML2, C TRACED0, D DCD2.
89 PD3 bidirectional PIO line PD3, reset PIO input with pull-up and Schmitt trigger; A GTX1, B PWMC1_PWMH1, C UTXD4, D RI0.
90 VDDPLLUSB power_in Supply for the UTMI PLL and the 3 to 20 MHz oscillator.
91 PD2 bidirectional PIO line PD2, reset PIO input with pull-up and Schmitt trigger; A GTX0, B PWMC1_PWML1, C SPI1_NPCS3, D DSR0.
92 PD1 bidirectional PIO line PD1, reset PIO input with pull-up and Schmitt trigger; A GTXEN, B PWMC1_PWMH0, C SPI1_NPCS2, D DTR0.
93 VDDUTMII power_in USB transceiver interface supply; must be connected to VDDIO.
94 HSDM bidirectional USB high-speed data minus line (USBHS HSDM) on the VDDUTMII rail.
95 HSDP bidirectional USB high-speed data plus line (USBHS HSDP) on the VDDUTMII rail.
96 VDDUTMIC power_in USB transceiver core supply.
97 VBG passive Bandgap voltage reference pin (VBG) on the analog side.
98 PB8 bidirectional PIO line PB8 used as XOUT, the main crystal oscillator output (selection independent of PIO configuration), with PIO high-impedance at reset.
99 PB9 bidirectional PIO line PB9 used as XIN, the main crystal oscillator input (selection independent of PIO configuration), with PIO high-impedance at reset.
100 PB13 bidirectional PIO line PB13, reset PIO input with pull-up and Schmitt trigger; alternate DAC0 (DAC output, footnote 11), A PWMC0_PWML2, B PCK0, C SCK0.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Single supply voltage (Industrial Temperature Devices) 1.7 3.6 V for Industrial Temperature Devices 2

CAD (KiCad official)

  • Symbol: ATSAME70N21B-ANT
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: atsame70n21b-ant-etched.step / atsame70n21b-ant-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsame70n21b-ant.step / atsame70n21b-ant.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1943 pp, sha256 94ed9d6997caca1c, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF