# ATSAME70J21B-AN

**Microchip Tech** · Pre-ordered MCUs · LQFP-64(10x10)

ATSAME70J21B-AN from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD0 | bidirectional | PIO line PD0 also carries DAC1 (selected when DACC_CHER.CH1 is set), GTXCK, PWMC1_PWML0 and DCD0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 2 | PD31 | bidirectional | PIO line PD31 also carries QIO3, UTXD3, PCK2 and ISI_D11; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 3 | VDDOUT | power_out | Voltage regulator output; the schematic checklist recommends 100 nF + 1 µF decoupling. |
| 4 | VDDIN | power_in | Voltage regulator input that also supplies the ADC, DAC and analog comparator; VDDIN and VDDIO must have the same level and be higher than or equal to VDDCORE. |
| 5 | VREFP | power_in | AFE and DAC voltage reference input (VDDIO rail); it must rise simultaneously with VDDIO and VDDIN to prevent overcurrent at powerup. |
| 6 | GND | power_in | Ground pin for the core, voltage regulator and peripheral I/O; connect as shortly as possible to the system ground plane. |
| 7 | PB1 | bidirectional | PIO line PB1 also carries AFE1_AD0/RTCOUT1 (analog input has priority over RTCOUT1), PWMC0_PWMH1, GTSUCOMP, TXD0 and TK; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 8 | PB0 | bidirectional | PIO line PB0 also carries AFE0_AD10/RTCOUT0 (analog input has priority over RTCOUT0), PWMC0_PWMH0, RXD0 and TF; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 9 | PB2 | bidirectional | PIO line PB2 also carries AFE0_AD5 (analog input), CANTX0, CTS0 and SPI0_NPCS0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 10 | VDDIO | power_in | Supplies the peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz crystal oscillator and oscillator pads; for USB operation VDDIO must be between 3.0 V and 3.6 V. |
| 11 | PB3 | bidirectional | PIO line PB3 also carries AFE0_AD2/WKUP12 (analog input has priority over WKUP12), CANRX0, PCK2, RTS0 and ISI_D2; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 12 | PA21 | bidirectional | PIO line PA21 also carries AFE0_AD1/PIODCEN2 (analog input has priority over WKUP), RXD1, PCK1 and PWMC1_PWMFI0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 13 | VDDCORE | power_in | Supplies the core, embedded memories and peripherals; VDDIN and VDDIO must always be higher than or equal to VDDCORE. |
| 14 | GND | power_in | Ground pin for the core, voltage regulator and peripheral I/O; connect as shortly as possible to the system ground plane. |
| 15 | PA7 | bidirectional | PIO line PA7 is used as the 32.768 kHz crystal oscillator input XIN32 (also PWMC0_PWMH3); it resets as PIO with high impedance. |
| 16 | PA8 | bidirectional | PIO line PA8 is used as the 32.768 kHz crystal oscillator output XOUT32 (also PWMC1_PWMH3 and AFE0_ADTRG); it resets as PIO with high impedance. |
| 17 | PA22 | bidirectional | PIO line PA22 carries the parallel capture clock PIODCCLK, RK and PWMC0_PWMEXTRG1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 18 | PA13 | bidirectional | PIO line PA13 also carries PIODC7, QIO0, PWMC0_PWMH2 and PWMC1_PWML1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 19 | PA14 | bidirectional | PIO line PA14 also carries WKUP8/PIODCEN1, QSCK, PWMC0_PWMH3 and PWMC1_PWMH1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 20 | PD25 | bidirectional | PIO line PD25 also carries PWMC0_PWML1, SPI0_NPCS1, URXD2 and ISI_VSYNC; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 21 | PD26 | bidirectional | PIO line PD26 also carries PWMC0_PWML2, TD, UTXD2 and UTXD1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 22 | PD24 | bidirectional | PIO line PD24 also carries PWMC0_PWML0, RF, TCLK11 and ISI_HSYNC; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 23 | PA24 | bidirectional | PIO line PA24 also carries RTS1, PWMC0_PWMH1, A20 and ISI_PCK; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 24 | VDDCORE | power_in | Supplies the core, embedded memories and peripherals; VDDIN and VDDIO must always be higher than or equal to VDDCORE. |
| 25 | PD22 | bidirectional | PIO line PD22 also carries PWMC0_PWMH2, SPI0_SPCK, TIOB11 and ISI_D0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 26 | PD21 | bidirectional | PIO line PD21 also carries PWMC0_PWMH1, SPI0_MOSI, TIOA11 and ISI_D1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 27 | PA11 | bidirectional | PIO line PA11 also carries WKUP7/PIODC5, QCS, PWMC0_PWMH0 and PWMC1_PWML0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 28 | PA10 | bidirectional | PIO line PA10 also carries PIODC4, UTXD0, PWMC0_PWMEXTRG0 and RD; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 29 | PA12 | bidirectional | PIO line PA12 also carries PIODC6, QIO1, PWMC0_PWMH1 and PWMC1_PWMH0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 30 | PA27 | bidirectional | PIO line PA27 also carries DTR1, TIOB2 and ISI_D7; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 31 | GND | power_in | Ground pin for the core, voltage regulator and peripheral I/O; connect as shortly as possible to the system ground plane. |
| 32 | PA5 | bidirectional | PIO line PA5 also carries WKUP4/PIODC2, PWMC1_PWML3, ISI_D4 and URXD1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 33 | PA9 | bidirectional | PIO line PA9 also carries WKUP6/PIODC3, URXD0, ISI_D3 and PWMC0_PWMFI0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 34 | PA4 | bidirectional | PIO line PA4 also carries WKUP3/PIODC1, TWCK0, TCLK0 and UTXD1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 35 | PB6 | bidirectional | PIO line PB6 is multiplexed with SWDIO/TMS (Serial Wire Debug / JTAG mode select); it resets as a PIO input with Schmitt trigger and no internal pull-up. |
| 36 | NRST | bidirectional | Microcontroller reset input/output, active low, with internal pull-up enabled at reset. |
| 37 | TST | input | Test select input used for JTAG boundary scan or Fast Flash Programming; it has an internal ~15 kΩ pull-down to GND and can be left unconnected. |
| 38 | PB12 | bidirectional | PIO line PB12 is multiplexed with ERASE (low level at startup is mandatory when ERASE mode is not used) and also carries PWMC0_PWML1, GTSUCOMP and PCK0; it resets as a PIO input with pull-down and Schmitt trigger. |
| 39 | PB7 | bidirectional | PIO line PB7 is multiplexed with SWCLK/TCK (Serial Wire Clock / JTAG test clock); it resets as a PIO input with Schmitt trigger and no internal pull-up. |
| 40 | PA3 | bidirectional | PIO line PA3 also carries PIODC0, TWD0, LONCOL1 and PCK2; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 41 | PD12 | bidirectional | PIO line PD12 also carries GRX3 and ISI_D6; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 42 | VDDIO | power_in | Supplies the peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz crystal oscillator and oscillator pads; for USB operation VDDIO must be between 3.0 V and 3.6 V. |
| 43 | PD11 | bidirectional | PIO line PD11 also carries GRX2, PWMC0_PWMH0, GTSUCOMP and ISI_D5; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 44 | PD10 | bidirectional | PIO line PD10 also carries GCRS, PWMC0_PWML0, TD and MLBSIG; it resets as a PIO input with pull-down and Schmitt trigger enabled. |
| 45 | JTAGSEL | input | JTAG selection input; a high level selects JTAG boundary scan, has an internal ~15 kΩ pull-down to GND, and a chip reset is required after it is changed. |
| 46 | PB4 | bidirectional | PIO line PB4 is multiplexed with TDI (JTAG boundary scan data input) and also carries TWD1, PWMC0_PWMH2, MLBCLK and TXD1; it resets as a PIO input with pull-down and Schmitt trigger. |
| 47 | PB5 | bidirectional | PIO line PB5 is multiplexed with TDO/TRACESWO (JTAG data out / trace output) and also carries TWCK1, PWMC0_PWML0 and MLBDAT; it resets as an output with pull-up. |
| 48 | PD9 | bidirectional | PIO line PD9 also carries GMDIO, PWMC0_PWMFI2 and AFE1_ADTRG; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 49 | PD8 | bidirectional | PIO line PD8 also carries GMDC, PWMC0_PWMFI1 and TRACECLK; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 50 | PD7 | bidirectional | PIO line PD7 also carries GRXER, PWMC1_PWMH3 and TRACED3; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 51 | PD6 | bidirectional | PIO line PD6 also carries GRX1, PWMC1_PWML3 and TRACED2; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 52 | VDDPLL | power_in | Supplies PLLA and the fast RC oscillator; VDDCORE, VDDPLL and VDDUTMIC voltage levels must not vary by more than 0.6 V. |
| 53 | PD5 | bidirectional | PIO line PD5 also carries GRX0, PWMC1_PWMH2 and TRACED1; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 54 | PD4 | bidirectional | PIO line PD4 also carries GRXDV, PWMC1_PWML2 and TRACED0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 55 | PD3 | bidirectional | PIO line PD3 also carries GTX1, PWMC1_PWMH1, UTXD4 and RI0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 56 | PD2 | bidirectional | PIO line PD2 also carries GTX0, PWMC1_PWML1 and DSR0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 57 | PD1 | bidirectional | PIO line PD1 also carries GTXEN, PWMC1_PWMH0 and DTR0; it resets as a PIO input with pull-up and Schmitt trigger enabled. |
| 58 | VDDIO | power_in | Supplies the peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz crystal oscillator and oscillator pads; for USB operation VDDIO must be between 3.0 V and 3.6 V. |
| 59 | DM | bidirectional | USB High-Speed data minus line of the USBHS interface (480 Mbps), powered from VDDUTMII which must be connected to VDDIO. |
| 60 | DP | bidirectional | USB High-Speed data plus line of the USBHS interface (480 Mbps), powered from VDDUTMII which must be connected to VDDIO. |
| 61 | VDDCORE | power_in | Supplies the core, embedded memories and peripherals; VDDIN and VDDIO must always be higher than or equal to VDDCORE. |
| 62 | PB8 | bidirectional | PIO line PB8 is used as main crystal oscillator output XOUT (3 to 20 MHz); it may be left unconnected in bypass mode and resets as PIO with high impedance. |
| 63 | PB9 | bidirectional | PIO line PB9 is used as main crystal oscillator input XIN (3 to 20 MHz); in bypass mode an external clock up to 20 MHz is applied and it resets as PIO with high impedance. |
| 64 | VDDPLLUSB | power_in | Supplies the UTMI PLL and the 3 to 20 MHz oscillator; it is noise sensitive, and VDDPLLUSB, VDDUTMII, VDDIN and VDDIO must be at least 3.0 V for USB operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Single supply voltage (Industrial temperature devices) |  | 1.7 |  | 3.6 | V | Industrial Temperature Devices | 2 |
| Operating temperature range (Industrial N grade) |  | -40 |  | 105 | °C | Industrial (N) grade per ordering information | 15 |
| VDDIO voltage range for USB operations | VDDIO | 3 |  | 3.6 | V | For USB operations | 43 |
| Supply requirement for USB operation (VDDUTMII, VDDPLLUSB, VDDIN, VDDIO) | VDDUTMII, VDDPLLUSB, VDDIN, VDDIO | 3 |  |  | V | For the USB to be operational | 43 |
| Maximum variation between VDDCORE, VDDPLL and VDDUTMIC levels | VDDCORE, VDDPLL, VDDUTMIC |  |  | 0.6 | V | Voltage levels must not vary by more than 0.6 V | 43 |

## CAD (KiCad official)

- Symbol: `ATSAME70J21B-AN`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `atsame70j21b-an-etched.step` / `atsame70j21b-an-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atsame70j21b-an.step` / `atsame70j21b-an.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/atsame70j21b-an-datasheet.pdf) (1943 pp, sha256 `94ed9d6997caca1c`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/atsame70j21b-an-datasheet.pdf)