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ATSAME51J19A-MU

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Microchip Tech Pre-ordered MCUs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ATSAME51J19A-MU

Microchip Tech · Pre-ordered MCUs · QFN-64-EP(9x9)

ATSAME51J19A-MU from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA00 bidirectional General-purpose I/O pin of PORT group A, also the XIN32 input of the XOSC32K crystal oscillator (Table 6-2).
2 PA01 bidirectional General-purpose I/O pin of PORT group A, also the XOUT32 output of the XOSC32K crystal oscillator (Table 6-2).
3 PA02 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[2], ADC0 AIN[0] and DAC VOUT[0] (Table 6-1).
4 PA03 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[3], ANAREF VREFA and ADC0 AIN[1] (Table 6-1).
5 PB04 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[4] and ADC1 AIN[6] (Table 6-1).
6 PB05 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[5] and ADC1 AIN[7] (Table 6-1).
7 GNDANA power_in Ground for the analog circuitry (ADC, DAC, analog comparators).
8 VDDANA power_in Analog supply pin for the ADC, DAC and analog peripherals.
9 PB06 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[6], ADC1 AIN[8] and PTC X24/Y24 (Table 6-1).
10 PB07 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[7], ADC1 AIN[9] and PTC X25/Y25 (Table 6-1).
11 PB08 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[8], ADC0 AIN[2], ADC1 AIN[0] and SERCOM4 PAD[0] (Table 6-1).
12 PB09 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[9], ADC0 AIN[3] and ADC1 AIN[1] (Table 6-1).
13 PA04 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[4], ANAREF VREFB and ADC0 AIN[4] (Table 6-1).
14 PA05 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[5], ADC0 AIN[5] and DAC VOUT[1] (Table 6-1).
15 PA06 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[6], ANAREF VREFC and ADC0 AIN[6] (Table 6-1).
16 PA07 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[7] and ADC0 AIN[7] (Table 6-1).
17 PA08 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with EIC NMI and ADC0 AIN[8] (Table 6-1, note 3).
18 PA09 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[9] and ADC0 AIN[9] (Table 6-1, note 3).
19 PA10 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[10] and ADC0 AIN[10] (Table 6-1).
20 PA11 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[11] and ADC0 AIN[11] (Table 6-1).
21 VDDIOB power_in Supply pin for the I/O group B pads, as listed in the SERCOM I2C configuration table (Table 6-8).
22 GND power_in Digital ground pin.
23 PB10 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[10], SERCOM4 PAD[2] and GCLK IO[4] (Table 6-1).
24 PB11 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[11], SERCOM4 PAD[3] and GCLK IO[5] (Table 6-1).
25 PB12 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[12] and CAN1 TX (Table 6-1).
26 PB13 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[13] and CAN1 RX (Table 6-1).
27 PB14 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[14] and GMAC GMDC (Table 6-1).
28 PB15 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[15] and GMAC GMDIO (Table 6-1).
29 PA12 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with SERCOM2 PAD[0] and QSPI DATA[0] (Table 6-1, note 3).
30 PA13 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with SERCOM2 PAD[1] and QSPI DATA[1] (Table 6-1, note 3).
31 PA14 bidirectional General-purpose I/O pin of PORT group A, also the XIN input of XOSC0 (Table 6-2).
32 PA15 bidirectional General-purpose I/O pin of PORT group A, also the XOUT output of XOSC0 (Table 6-2).
33 GND power_in Digital ground pin.
34 VDDIO power_in Supply pin for the main I/O group, which supplies the oscillator and SWD pins as listed in Tables 6-2 and 6-4.
35 PA16 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with SERCOM1 PAD[0], GRXDV (64-pin only) and EIC EXTINT[0] (Table 6-1, notes 3 and 6).
36 PA17 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with SERCOM1 PAD[1] and EIC EXTINT[1] (Table 6-1, note 3).
37 PA18 bidirectional General-purpose I/O pin of PORT group A, multiplexed with SERCOM1 PAD[2] and EIC EXTINT[2] (Table 6-1).
38 PA19 bidirectional General-purpose I/O pin of PORT group A, multiplexed with SERCOM1 PAD[3] and EIC EXTINT[3] (Table 6-1).
39 PB16 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[0] and SERCOM5 PAD[0] (Table 6-1).
40 PB17 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[1] and SERCOM5 PAD[1] (Table 6-1).
41 PA20 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[4], SERCOM3 PAD[2] and PCC DATA[4] (Table 6-1).
42 PA21 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[5], SERCOM3 PAD[3] and PCC DATA[5] (Table 6-1).
43 PA22 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[6], SERCOM3 PAD[0] and CAN0 TX (Table 6-1, note 3).
44 PA23 bidirectional High-sink general-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[7], SERCOM3 PAD[1] and CAN0 RX (Table 6-1, note 3).
45 PA24 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[8], SERCOM3 PAD[2] and USB DM (Table 6-1).
46 PA25 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[9], SERCOM3 PAD[3] and USB DP (Table 6-1).
47 GND power_in Digital ground pin.
48 VDDIO power_in Supply pin for the main I/O group.
49 PB22 bidirectional General-purpose I/O pin of PORT group B, also the XIN input of XOSC1 (Table 6-2).
50 PB23 bidirectional General-purpose I/O pin of PORT group B, also the XOUT output of XOSC1 (Table 6-2).
51 PA27 bidirectional General-purpose I/O pin of PORT group A, multiplexed with EIC EXTINT[11] and GCLK IO[1] (Table 6-1).
52 RESETN input External active-low reset input pin of the device.
53 VDDCORE power_in Core supply pin for the internal logic, fed from the regulator (Section 7 power supply considerations).
54 GND power_in Digital ground pin.
55 VSW power_out Switching node of the embedded buck regulator, used with the external inductor and VDDCORE.
56 VDDIO power_in Supply pin for the main I/O group.
57 PA30 bidirectional General-purpose I/O pin of PORT group A, also the SWCLK serial-wire debug clock (Table 6-4).
58 PA31 bidirectional General-purpose I/O pin of PORT group A, also the SWDIO serial-wire debug data pin (Table 6-4).
59 PB30 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[14] and the SWO trace output (Table 6-1, note 5).
60 PB31 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[15] and SERCOM7/SERCOM5 PAD[1] (Table 6-1).
61 PB00 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[0], ADC0 AIN[12] and PTC X30/Y30 (Table 6-1).
62 PB01 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[1], ADC0 AIN[13] and PTC X31/Y31 (Table 6-1).
63 PB02 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[2], ADC0 AIN[14] and PTC X20/Y20 (Table 6-1).
64 PB03 bidirectional General-purpose I/O pin of PORT group B, multiplexed with EIC EXTINT[3], ADC0 AIN[15] and PTC X21/Y21 (Table 6-1).
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Embedded Processors & Controllers
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDIO and VDDANA (VDD) VDD 1.71 3.63 V Operating Conditions: 1.71V to 3.63V, -40°C to +85°C, DC to 120 MHz 1
Supply voltage VDDIOB VDDIOB 1.71 3.63 V Powers I/O B lines; must be equal to or lower than VDDIO 46
Supply voltage VBAT VBAT 1.71 3.63 V Powers the Automatic Power Switch 46
Operating temperature range (grade U, 120 MHz) -40 85 °C Operating Conditions: -40°C to +85°C, DC to 120 MHz 1
Internal regulator output voltage VDDCORE VDDCORE 1.2 V Voltage is 1.2V typical (linear regulator output) 46

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pet nu1RBase nu1 I Crypto RAM u2RLength Base of R Base of R value filled repetitively with u4FillValue 1316
contacts tin including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In the Self Capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. 1697

CAD (KiCad official)

  • Symbol: ATSAME51J19A-MU
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: atsame51j19a-mu-etched.step / atsame51j19a-mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsame51j19a-mu.step / atsame51j19a-mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1934 pp, sha256 6f02ccc3e69325ab, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF