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ATSAMDA1J16B-ABT

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ATSAMDA1J16B-ABT

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

ATSAMDA1J16B-ABT from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA00 bidirectional Port A digital I/O on the VDDANA domain with EXTINT[0], AIN[0] and Y[0] functions, and XIN32 32 kHz crystal input when XOSC32K is used.
2 PA01 bidirectional Port A digital I/O on the VDDANA domain with EXTINT[1] and AIN[1] functions, and XOUT32 32 kHz crystal output when XOSC32K is used.
3 PA02 bidirectional Port A I/O on the VDDANA domain with EXTINT[2], AIN[0] analog input and DAC VOUT output.
4 PA03 bidirectional Port A I/O on the VDDANA domain with EXTINT[3], AIN[1] analog input and ADC/DAC VREFA reference function.
5 PB04 bidirectional Port B I/O on the VDDANA domain with EXTINT[4], AIN[12] analog input and PTC Y[10].
6 PB05 bidirectional Port B I/O on the VDDANA domain with EXTINT[5], AIN[13] analog input and PTC Y[11].
7 GNDANA power_in Ground pin for the analog section, paired with VDDANA.
8 VDDANA power_in Analog supply pin for the ADC, DAC, analog comparators and VDDANA-domain pins.
9 PB06 bidirectional Port B I/O on the VDDANA domain with EXTINT[6], AIN[14] analog input and PTC Y[12].
10 PB07 bidirectional Port B I/O on the VDDANA domain with EXTINT[7], AIN[15] analog input and PTC Y[13].
11 PB08 bidirectional Port B I/O on the VDDANA domain with EXTINT[8], AIN[2] analog input, PTC Y[14] and SERCOM4 PAD[0].
12 PB09 bidirectional Port B I/O on the VDDANA domain with EXTINT[9], AIN[3] analog input, PTC Y[15] and SERCOM4 PAD[1].
13 PA04 bidirectional Port A I/O on the VDDANA domain with EXTINT[4], AIN[4] and AIN[0] analog inputs, ADC/VREFB and SERCOM0 PAD[0].
14 PA05 bidirectional Port A I/O on the VDDANA domain with EXTINT[5], AIN[5] and AIN[1] analog inputs and SERCOM0 PAD[1].
15 PA06 bidirectional Port A I/O on the VDDANA domain with EXTINT[6], AIN[6] and AIN[2] analog inputs and SERCOM0 PAD[2].
16 PA07 bidirectional Port A I/O on the VDDANA domain with EXTINT[7], AIN[7] and AIN[3] analog inputs and SERCOM0 PAD[3].
17 PA08 bidirectional Port A I/O on the VDDIO domain with NMI, AIN[16] analog input, PTC X[0] and SERCOM0/SERCOM2 PAD[0].
18 PA09 bidirectional Port A I/O on the VDDIO domain with EXTINT[9], AIN[17] analog input, PTC X[1] and SERCOM0/SERCOM2 PAD[1].
19 PA10 bidirectional Port A I/O on the VDDIO domain with EXTINT[10], AIN[18] analog input, PTC X[2] and SERCOM0/SERCOM2 PAD[2].
20 PA11 bidirectional Port A I/O on the VDDIO domain with EXTINT[11], AIN[19] analog input, PTC X[3] and SERCOM0/SERCOM2 PAD[3].
21 VDDIO power_in I/O supply pin for the VDDIO-domain digital pins.
22 GND power_in Digital ground pin.
23 PB10 bidirectional Port B I/O on the VDDIO domain with EXTINT[10], SERCOM4 PAD[2], TC5 WO[0] and I2S MCK[1].
24 PB11 bidirectional Port B I/O on the VDDIO domain with EXTINT[11], SERCOM4 PAD[3], TC5 WO[1] and I2S SCK[1].
25 PB12 bidirectional Port B I/O on the VDDIO domain with EXTINT[12], PTC X[12], SERCOM4 PAD[0] and I2S FS[1].
26 PB13 bidirectional Port B I/O on the VDDIO domain with EXTINT[13], PTC X[13] and SERCOM4 PAD[1].
27 PB14 bidirectional Port B I/O on the VDDIO domain with EXTINT[14], PTC X[14], SERCOM4 PAD[2] and TC5 WO[0].
28 PB15 bidirectional Port B I/O on the VDDIO domain with EXTINT[15], PTC X[15], SERCOM4 PAD[3] and TC5 WO[1].
29 PA12 bidirectional Port A I/O on the VDDIO domain with EXTINT[12], SERCOM2/SERCOM4 PAD[0], TCC2 WO[0] and AC CMP[0].
30 PA13 bidirectional Port A I/O on the VDDIO domain with EXTINT[13], SERCOM2/SERCOM4 PAD[1], TCC2 WO[1] and AC CMP[1].
31 PA14 bidirectional Port A I/O on the VDDIO domain with EXTINT[14], SERCOM2/SERCOM4 PAD[2] and TC3 WO[0]; XIN crystal input when XOSC is used.
32 PA15 bidirectional Port A I/O on the VDDIO domain with EXTINT[15], SERCOM2/SERCOM4 PAD[3] and TC3 WO[1]; XOUT crystal output when XOSC is used.
33 GND power_in Digital ground pin.
34 VDDIO power_in I/O supply pin for the VDDIO-domain digital pins.
35 PA16 bidirectional Port A I/O on the VDDIO domain with EXTINT[0], PTC X[4], SERCOM1/SERCOM3 PAD[0] and TCC2 WO[0].
36 PA17 bidirectional Port A I/O on the VDDIO domain with EXTINT[1], PTC X[5], SERCOM1/SERCOM3 PAD[1] and TCC2 WO[1].
37 PA18 bidirectional Port A I/O on the VDDIO domain with EXTINT[2], PTC X[6], SERCOM1/SERCOM3 PAD[2], TC3 WO[0] and AC CMP[0].
38 PA19 bidirectional Port A I/O on the VDDIO domain with EXTINT[3], PTC X[7], SERCOM1/SERCOM3 PAD[3], TC3 WO[1] and AC CMP[1].
39 PB16 bidirectional Port B I/O on the VDDIO domain with EXTINT[0], SERCOM5 PAD[0], TC6 WO[0] and I2S SD[1].
40 PB17 bidirectional Port B I/O on the VDDIO domain with EXTINT[1], SERCOM5 PAD[1], TC6 WO[1] and I2S MCK[0].
41 PA20 bidirectional Port A I/O on the VDDIO domain with EXTINT[4], PTC X[8], SERCOM5/SERCOM3 PAD[2] and TC7 WO[0].
42 PA21 bidirectional Port A I/O on the VDDIO domain with EXTINT[5], PTC X[9], SERCOM5/SERCOM3 PAD[3] and TC7 WO[1].
43 PA22 bidirectional Port A I/O on the VDDIO domain with EXTINT[6], PTC X[10], SERCOM3/SERCOM5 PAD[0] and TC4 WO[0].
44 PA23 bidirectional Port A I/O on the VDDIO domain with EXTINT[7], PTC X[11], SERCOM3/SERCOM5 PAD[1] and USB SOF 1kHz output.
45 PA24 bidirectional Port A I/O on the VDDIO domain with EXTINT[12], SERCOM3/SERCOM5 PAD[2], TC5 WO[0] and USB DM; has no drive strength option and a pull-up is recommended if unconnected.
46 PA25 bidirectional Port A I/O on the VDDIO domain with EXTINT[13], SERCOM3/SERCOM5 PAD[3], TC5 WO[1] and USB DP; has no drive strength option and a pull-up is recommended if unconnected.
47 GND power_in Digital ground pin.
48 VDDIO power_in I/O supply pin for the VDDIO-domain digital pins.
49 PB22 bidirectional Port B I/O on the VDDIO domain with EXTINT[6], SERCOM5 PAD[2], TC7 WO[0] and TCC3 WO[0].
50 PB23 bidirectional Port B I/O on the VDDIO domain with EXTINT[7], SERCOM5 PAD[3], TC7 WO[1] and TCC3 WO[1].
51 PA27 bidirectional Port A I/O on the VDDIO domain with EXTINT[15], TCC3 WO[6] and GCLK_IO[0].
52 RESET input External active-low reset input.
53 PA28 bidirectional Port A I/O on the VDDIO domain with EXTINT[8], TCC3 WO[7] and GCLK_IO[0].
54 GND power_in Digital ground pin.
55 VDDCORE power_in Regulated output of the internal voltage regulator that supplies the core.
56 VDDIN power_in Input supply pin for the internal voltage regulator.
57 PA30 bidirectional Port A I/O on the VDDIO domain with EXTINT[10], SERCOM1 PAD[2], TCC1 WO[0] and SWCLK debug clock input.
58 PA31 bidirectional Port A I/O on the VDDIO domain with EXTINT[11], SERCOM1 PAD[3], TCC1 WO[1] and SWDIO debug data, active only when a debugger is present.
59 PB30 bidirectional Port B I/O on the VDDIO domain with EXTINT[14], SERCOM5 PAD[0], TCC0 WO[0] and TCC1 WO[2].
60 PB31 bidirectional Port B I/O on the VDDIO domain with EXTINT[15], SERCOM5 PAD[1], TCC0 WO[1] and TCC1 WO[3].
61 PB00 bidirectional Port B I/O on the VDDANA domain with EXTINT[0], AIN[8] analog input, PTC Y[6] and SERCOM5 PAD[2].
62 PB01 bidirectional Port B I/O on the VDDANA domain with EXTINT[1], AIN[9] analog input, PTC Y[7] and SERCOM5 PAD[3].
63 PB02 bidirectional Port B I/O on the VDDANA domain with EXTINT[2], AIN[10] analog input, PTC Y[8] and SERCOM5 PAD[0].
64 PB03 bidirectional Port B I/O on the VDDANA domain with EXTINT[3], AIN[11] analog input, PTC Y[9] and SERCOM5 PAD[1].

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage (SAM DA1) 2.7 3.63 V SAM DA1 operating voltage as printed in Features 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In the self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. 859

CAD (KiCad official)

  • Symbol: ATSAMDA1J16B-ABT
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: atsamda1j16b-abt-etched.step / atsamda1j16b-abt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsamda1j16b-abt.step / atsamda1j16b-abt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1148 pp, sha256 18ca1ccab5aa330f, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF