ATSAMD21J17D-MU from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PA00	bidirectional	Port A pin PA00 on the VDDANA supply domain; it is the XIN32 32 kHz crystal input when XOSC32K is used (Table 7-3).
2	PA01	bidirectional	Port A pin PA01 on the VDDANA supply domain; it is the XOUT32 32 kHz crystal output when XOSC32K is used (Table 7-3).
3	PA02	bidirectional	Port A pin PA02 on the VDDANA supply domain, with analog input AIN[0] and DAC output VOUT on peripheral function B (Table 7-1).
4	PA03	bidirectional	Port A pin PA03 on the VDDANA supply domain, with analog input AIN[1] and ADC/DAC voltage reference VREFA on peripheral function B (Table 7-1).
5	PB04	bidirectional	Port B pin PB04 on the VDDANA supply domain, with analog input AIN[12] on peripheral function B (Table 7-1).
6	PB05	bidirectional	Port B pin PB05 on the VDDANA supply domain, with analog input AIN[13] on peripheral function B (Table 7-1).
7	GNDANA	power_in	Ground for the analog domain, paired with VDDANA pin 8.
8	VDDANA	power_in	Analog supply for the analog peripherals, paired with GNDANA pin 7.
9	PB06	bidirectional	Port B pin PB06 on the VDDANA supply domain, with analog input AIN[14] on peripheral function B (Table 7-1).
10	PB07	bidirectional	Port B pin PB07 on the VDDANA supply domain, with analog input AIN[15] on peripheral function B (Table 7-1).
11	PB08	bidirectional	Port B pin PB08 on the VDDANA supply domain, with analog input AIN[2] on peripheral function B (Table 7-1).
12	PB09	bidirectional	Port B pin PB09 on the VDDANA supply domain, with analog input AIN[3] on peripheral function B (Table 7-1).
13	PA04	bidirectional	Port A pin PA04 on the VDDANA supply domain, with analog input AIN[4] and ADC voltage reference VREFB on peripheral function B (Table 7-1).
14	PA05	bidirectional	Port A pin PA05 on the VDDANA supply domain, with analog input AIN[5] on peripheral function B (Table 7-1).
15	PA06	bidirectional	Port A pin PA06 on the VDDANA supply domain, with analog input AIN[6] on peripheral function B (Table 7-1).
16	PA07	bidirectional	Port A pin PA07 on the VDDANA supply domain, with analog input AIN[7] on peripheral function B (Table 7-1).
17	PA08	bidirectional	Port A pin PA08 on the VDDIO supply domain, with NMI and analog input AIN[16] on peripheral function B (Table 7-1).
18	PA09	bidirectional	Port A pin PA09 on the VDDIO supply domain, with analog input AIN[17] on peripheral function B (Table 7-1).
19	PA10	bidirectional	Port A pin PA10 on the VDDIO supply domain, with analog input AIN[18] on peripheral function B (Table 7-1).
20	PA11	bidirectional	Port A pin PA11 on the VDDIO supply domain, with analog input AIN[19] on peripheral function B (Table 7-1).
21	VDDIO	power_in	Supply for the digital I/O pins of this I/O bank, paired with GND pin 22.
22	GND	power_in	Digital ground paired with VDDIO pin 21.
23	PB10	bidirectional	Port B pin PB10 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
24	PB11	bidirectional	Port B pin PB11 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
25	PB12	bidirectional	Port B pin PB12 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
26	PB13	bidirectional	Port B pin PB13 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
27	PB14	bidirectional	Port B pin PB14 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
28	PB15	bidirectional	Port B pin PB15 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
29	PA12	bidirectional	Port A pin PA12 on the VDDIO supply domain, with analog comparator output AC/CMP[0] on peripheral function H (Table 7-1).
30	PA13	bidirectional	Port A pin PA13 on the VDDIO supply domain, with analog comparator output AC/CMP[1] on peripheral function H (Table 7-1).
31	PA14	bidirectional	Port A pin PA14 on the VDDIO supply domain; it is the XIN crystal input when XOSC is used (Table 7-3).
32	PA15	bidirectional	Port A pin PA15 on the VDDIO supply domain; it is the XOUT crystal output when XOSC is used (Table 7-3).
33	GND	power_in	Digital ground paired with VDDIO pin 34.
34	VDDIO	power_in	Supply for the digital I/O pins of this I/O bank, paired with GND pin 33.
35	PA16	bidirectional	Port A pin PA16 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
36	PA17	bidirectional	Port A pin PA17 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
37	PA18	bidirectional	Port A pin PA18 on the VDDIO supply domain, with analog comparator output AC/CMP[0] on peripheral function H (Table 7-1).
38	PA19	bidirectional	Port A pin PA19 on the VDDIO supply domain, with analog comparator output AC/CMP[1] on peripheral function H (Table 7-1).
39	PB16	bidirectional	Port B pin PB16 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
40	PB17	bidirectional	Port B pin PB17 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
41	PA20	bidirectional	Port A pin PA20 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
42	PA21	bidirectional	Port A pin PA21 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
43	PA22	bidirectional	Port A pin PA22 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
44	PA23	bidirectional	Port A pin PA23 on the VDDIO supply domain, with USB SOF 1kHz output on peripheral function H (Table 7-1).
45	PA24	bidirectional	Port A pin PA24 on the VDDIO supply domain, used as USB DM; if unconnected, a pull-up is recommended (Table 7-1 note 6).
46	PA25	bidirectional	Port A pin PA25 on the VDDIO supply domain, used as USB DP; if unconnected, a pull-up is recommended (Table 7-1 note 6).
47	GND	power_in	Digital ground paired with VDDIO pin 48.
48	VDDIO	power_in	Supply for the digital I/O pins of this I/O bank, paired with GND pin 47.
49	PB22	bidirectional	Port B pin PB22 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
50	PB23	bidirectional	Port B pin PB23 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
51	PA27	bidirectional	Port A pin PA27 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
52	RESET	input	External active-low reset input for the device.
53	PA28	bidirectional	Port A pin PA28 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
54	GND	power_in	Digital ground paired with VDDIN pin 56.
55	VDDCORE	power_out	Regulated output supply of the internal voltage regulator for the core.
56	VDDIN	power_in	Input supply for the device and internal voltage regulator, paired with GND pin 54.
57	PA30	bidirectional	Port A pin PA30 on the VDDIO supply domain; it is the SWCLK Serial Wire Debug clock (Table 7-4).
58	PA31	bidirectional	Port A pin PA31 on the VDDIO supply domain; it is the SWDIO Serial Wire Debug data pin (Table 7-4).
59	PB30	bidirectional	Port B pin PB30 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
60	PB31	bidirectional	Port B pin PB31 on the VDDIO supply domain, with peripheral multiplexing per Table 7-1.
61	PB00	bidirectional	Port B pin PB00 on the VDDANA supply domain, with analog input AIN[8] on peripheral function B (Table 7-1).
62	PB01	bidirectional	Port B pin PB01 on the VDDANA supply domain, with analog input AIN[9] on peripheral function B (Table 7-1).
63	PB02	bidirectional	Port B pin PB02 on the VDDANA supply domain, with analog input AIN[10] on peripheral function B (Table 7-1).
64	PB03	bidirectional	Port B pin PB03 on the VDDANA supply domain, with analog input AIN[11] on peripheral function B (Table 7-1).
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64-EP(9x9)
Category	Embedded Processors & Controllers
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Max	Unit	Conditions	Page
VDDIO supply voltage	VDDIO	1.62	3.63	V	Voltage range as stated in section 8.2.1 (VDDIO powers I/O lines, OSC8M and XOSC)	35
VDDIN supply voltage	VDDIN	1.62	3.63	V	Voltage range as stated in section 8.2.1 (VDDIN powers I/O lines and internal regulator)	35
VDDANA supply voltage	VDDANA	1.62	3.63	V	Voltage range as stated in section 8.2.1 (VDDANA powers I/O lines, ADC, AC, DAC, PTC, oscillators)	35

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In the self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor.	859

CAD (KiCad official)

Symbol: ATSAMD21J17D-MU
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: atsamd21j17d-mu-etched.step / atsamd21j17d-mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsamd21j17d-mu.step / atsamd21j17d-mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (1148 pp, sha256 18ca1ccab5aa330f, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ATSAMD21J17D-MU

Verified ATSAMD21J17D-MU

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README