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ATSAMD20E18A-MU

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Microchip Tech Pre-ordered MCUs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatsamd20e18a-mufactory-2.0.0extractor-text

Verified ATSAMD20E18A-MU

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAMD20E18A-MU · QFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 51-page datasheet
  • ✓distributor: lcsc C1338707, digikey ATSAMD20E18A-MU-ND, mouser 556-ATSAMD20E18A-MU
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lbgr7ggk/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atsamd20e18a-mu.kicad_sym✓ atsamd20e18a-mu.kicad_mod✓ atsamd20e18a-mu.step
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Ray Publish 0.1.0 d595bca 5d ago

ATSAMD20E18A-MU

Microchip Tech · Pre-ordered MCUs · QFN-32-EP(5x5)

ATSAMD20E18A-MU from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA00 bidirectional Port A I/O line PA00, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
2 PA01 bidirectional Port A I/O line PA01, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
3 PA02 bidirectional Port A I/O line PA02, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
4 PA03 bidirectional Port A I/O line PA03, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
5 PA04 bidirectional Port A I/O line PA04, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
6 PA05 bidirectional Port A I/O line PA05, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
7 PA06 bidirectional Port A I/O line PA06, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
8 PA07 bidirectional Port A I/O line PA07, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
9 VDDANA power_in Analog supply pin for the ADC, DAC, and analog comparators; the datasheet gives no voltage limit for this pin in the summary text.
10 GND power_in Digital ground pin.
11 PA08 bidirectional Port A I/O line PA08, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
12 PA09 bidirectional Port A I/O line PA09, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
13 PA10 bidirectional Port A I/O line PA10, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
14 PA11 bidirectional Port A I/O line PA11, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
15 PA14 bidirectional Port A I/O line PA14, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
16 PA15 bidirectional Port A I/O line PA15, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
17 PA16 bidirectional Port A I/O line PA16, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
18 PA17 bidirectional Port A I/O line PA17, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
19 PA18 bidirectional Port A I/O line PA18, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
20 PA19 bidirectional Port A I/O line PA19, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
21 PA22 bidirectional Port A I/O line PA22, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
22 PA23 bidirectional Port A I/O line PA23, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
23 PA24 bidirectional Port A I/O line PA24, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
24 PA25 bidirectional Port A I/O line PA25, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
25 PA27 bidirectional Port A I/O line PA27, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
26 RESET input Active reset pin of the device; the datasheet pinout marks it as the RESET pin without stating electrical limits in this summary.
27 PA28 bidirectional Port A I/O line PA28, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
28 GND power_in Digital ground pin.
29 VDDCORE power_out Output of the internal voltage regulator supplying the core; the datasheet pinout labels it as a regulated output supply.
30 VDDIN power_in Input supply pin for the device; the datasheet pinout labels it as an input supply, with the voltage range given in the operating-voltage feature (1.62 V to 3.63 V).
31 PA30 bidirectional Port A I/O line PA30, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
32 PA31 bidirectional Port A I/O line PA31, shown in the datasheet pinout as a digital pin of the 32-pin QFN package.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Voltage 1.62 3.63 V 2
Operating temperature (package grade U, ordering suffix -MU) -40 85 °C Package grade U, -40 to 85 °C matte Sn plating 6
Thermal resistance, junction-to-ambient, 32-pin QFN θJA 37.2 °C/W 32-pin QFN package 39
Thermal resistance, junction-to-case, 32-pin QFN θJC 13.1 °C/W 32-pin QFN package 39

CAD (KiCad official)

  • Symbol: ATSAMD20E18A-MU
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: atsamd20e18a-mu-etched.step / atsamd20e18a-mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsamd20e18a-mu.step / atsamd20e18a-mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (51 pp, sha256 71d57f206a04faff, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF