component
ATSAM4S4AA-MU
Public Made by Adomby adom
Microchip Tech Pre-ordered MCUs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
ATSAM4S4AA-MU
Microchip Tech · Pre-ordered MCUs · QFN-48-EP(7x7)
ATSAM4S4AA-MU from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADVREF | power_in | Reference voltage for the ADC, DAC and analog comparator. |
| 2 | GND | power_in | Ground. |
| 3 | PB0/AD4 | bidirectional | PIO line PB0 shared with ADC analog input AD4. |
| 4 | PB1/AD5 | bidirectional | PIO line PB1 shared with ADC analog input AD5. |
| 5 | PB2/AD6 | bidirectional | PIO line PB2 shared with ADC analog input AD6. |
| 6 | PB3/AD7 | bidirectional | PIO line PB3 shared with ADC analog input AD7. |
| 7 | VDDIN | power_in | Voltage regulator input and ADC, DAC and analog comparator supply, 1.62 to 3.6 V. |
| 8 | VDDOUT | power_out | Output of the internal voltage regulator. |
| 9 | PA17/PGMD5/AD0 | bidirectional | PIO line PA17 shared with FFPI data bit PGMD5 and ADC analog input AD0. |
| 10 | PA18/PGMD6/AD1 | bidirectional | PIO line PA18 shared with FFPI data bit PGMD6 and ADC analog input AD1. |
| 11 | PA19/PGMD7/AD2 | bidirectional | PIO line PA19 shared with FFPI data bit PGMD7 and ADC analog input AD2. |
| 12 | PA20/AD3 | bidirectional | PIO line PA20 shared with ADC analog input AD3. |
| 13 | VDDIO | power_in | Peripheral I/O lines supply, 1.62 to 3.6 V. |
| 14 | PA16/PGMD4 | bidirectional | PIO line PA16 shared with FFPI data bit PGMD4. |
| 15 | PA15/PGMD3 | bidirectional | PIO line PA15 shared with FFPI data bit PGMD3. |
| 16 | PA14/PGMD2 | bidirectional | PIO line PA14 shared with FFPI data bit PGMD2. |
| 17 | PA13/PGMD1 | bidirectional | PIO line PA13 shared with FFPI data bit PGMD1. |
| 18 | VDDCORE | power_in | Core, first flash rail, embedded memories and peripherals supply, 1.08 to 1.32 V. |
| 19 | PA12/PGMD0 | bidirectional | PIO line PA12 shared with FFPI data bit PGMD0. |
| 20 | PA11/PGMM3 | bidirectional | PIO line PA11 shared with FFPI programming mode input PGMM3. |
| 21 | PA10/PGMM2 | bidirectional | PIO line PA10 shared with FFPI programming mode input PGMM2. |
| 22 | PA9/PGMM1 | bidirectional | PIO line PA9 shared with FFPI programming mode input PGMM1. |
| 23 | PA8/XOUT32/PGMM0 | bidirectional | PIO line PA8 shared with 32 kHz crystal output XOUT32 and FFPI programming mode input PGMM0. |
| 24 | PA7/XIN32/PGMNVALID | bidirectional | PIO line PA7 shared with 32 kHz crystal input XIN32 and FFPI data direction output PGMNVALID. |
| 25 | TDI/PB4 | bidirectional | JTAG test data input shared with PIO line PB4; voltage must stay within -0.1 V to VDDIO+0.4 V per errata. |
| 26 | PA6/PGMNOE | bidirectional | PIO line PA6 shared with FFPI programming read input PGMNOE. |
| 27 | PA5/PGMRDY | bidirectional | PIO line PA5 shared with FFPI programming ready output PGMRDY. |
| 28 | PA4/PGMNCMD | bidirectional | PIO line PA4 shared with FFPI programming command input PGMNCMD. |
| 29 | NRST | bidirectional | Active-low microcontroller reset, input/output. |
| 30 | TST | input | Test select; low at power-up gives normal operation, high gives test or FFPI mode, with an internal pull-down of about 15 kΩ. |
| 31 | PA3 | bidirectional | PIO line PA3. |
| 32 | PA2/PGMEN2 | bidirectional | PIO line PA2 shared with FFPI programming enable input PGMEN2. |
| 33 | VDDIO | power_in | Peripheral I/O lines supply, 1.62 to 3.6 V. |
| 34 | GND | power_in | Ground. |
| 35 | PA1/PGMEN1 | bidirectional | PIO line PA1 shared with FFPI programming enable input PGMEN1. |
| 36 | PA0/PGMEN0 | bidirectional | PIO line PA0 shared with FFPI programming enable input PGMEN0. |
| 37 | TDO/TRACESWO/PB5 | output | JTAG test data out or asynchronous trace output TRACESWO (SW-DP only), shared with PIO line PB5. |
| 38 | JTAGSEL | input | Active-high JTAG selection input; a chip reset is required after it changes. |
| 39 | TMS/SWDIO/PB6 | bidirectional | JTAG test mode select or serial wire data I/O, shared with PIO line PB6. |
| 40 | TCK/SWCLK/PB7 | input | JTAG test clock or serial wire clock, shared with PIO line PB7. |
| 41 | VDDCORE | power_in | Core, first flash rail, embedded memories and peripherals supply, 1.08 to 1.32 V. |
| 42 | ERASE/PB12 | bidirectional | Flash erase input shared with PIO line PB12. |
| 43 | DDM/PB10 | bidirectional | USB full-speed data minus shared with PIO line PB10. |
| 44 | DDP/PB11 | bidirectional | USB full-speed data plus shared with PIO line PB11. |
| 45 | XOUT/PB8 | bidirectional | 3 to 20 MHz oscillator output shared with PIO line PB8. |
| 46 | XIN/PB9/PGMCK | bidirectional | 3 to 20 MHz oscillator input shared with PIO line PB9 and FFPI programming clock PGMCK. |
| 47 | VDDIO | power_in | Peripheral I/O lines supply, 1.62 to 3.6 V. |
| 48 | VDDPLL | power_in | Supply for PLLA, PLLB, fast RC and 3 to 20 MHz oscillator, 1.08 to 1.32 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range (ATSAM4S4AA-MU, MRL A, Industrial) | -40 | 85 | °C | Industrial (-40°C to +85°C) | 1221 | ||
| VDDIO supply voltage | VDDIO | 1.62 | 3.6 | V | Powers peripheral I/O lines, USB transceiver, backup part, 32 kHz oscillator | 27 | |
| VDDIN supply voltage | VDDIN | 1.62 | 3.6 | V | Voltage regulator input, ADC, DAC and analog comparator supply | 27 | |
| VDDCORE supply voltage | VDDCORE | 1.08 | 1.32 | V | Powers core, first flash rail, embedded memories and peripherals | 27 | |
| VDDPLL supply voltage | VDDPLL | 1.08 | 1.32 | V | Powers PLLA, PLLB, fast RC and 3 to 20 MHz oscillator | 27 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | before performing the calculation, making the base address for the calculation word-aligned. ̶ Note: To generate the address of an instruction, the constant based on the value of the PC must be | 118 |
CAD (KiCad official)
- Symbol:
ATSAM4S4AA-MU - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
atsam4s4aa-mu-etched.step/atsam4s4aa-mu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atsam4s4aa-mu.step/atsam4s4aa-mu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (1269 pp, sha256
64941c58dfa3899c, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATSAM4S4AA-MU
**Microchip Tech** · Pre-ordered MCUs · QFN-48-EP(7x7)
ATSAM4S4AA-MU from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADVREF | power_in | Reference voltage for the ADC, DAC and analog comparator. |
| 2 | GND | power_in | Ground. |
| 3 | PB0/AD4 | bidirectional | PIO line PB0 shared with ADC analog input AD4. |
| 4 | PB1/AD5 | bidirectional | PIO line PB1 shared with ADC analog input AD5. |
| 5 | PB2/AD6 | bidirectional | PIO line PB2 shared with ADC analog input AD6. |
| 6 | PB3/AD7 | bidirectional | PIO line PB3 shared with ADC analog input AD7. |
| 7 | VDDIN | power_in | Voltage regulator input and ADC, DAC and analog comparator supply, 1.62 to 3.6 V. |
| 8 | VDDOUT | power_out | Output of the internal voltage regulator. |
| 9 | PA17/PGMD5/AD0 | bidirectional | PIO line PA17 shared with FFPI data bit PGMD5 and ADC analog input AD0. |
| 10 | PA18/PGMD6/AD1 | bidirectional | PIO line PA18 shared with FFPI data bit PGMD6 and ADC analog input AD1. |
| 11 | PA19/PGMD7/AD2 | bidirectional | PIO line PA19 shared with FFPI data bit PGMD7 and ADC analog input AD2. |
| 12 | PA20/AD3 | bidirectional | PIO line PA20 shared with ADC analog input AD3. |
| 13 | VDDIO | power_in | Peripheral I/O lines supply, 1.62 to 3.6 V. |
| 14 | PA16/PGMD4 | bidirectional | PIO line PA16 shared with FFPI data bit PGMD4. |
| 15 | PA15/PGMD3 | bidirectional | PIO line PA15 shared with FFPI data bit PGMD3. |
| 16 | PA14/PGMD2 | bidirectional | PIO line PA14 shared with FFPI data bit PGMD2. |
| 17 | PA13/PGMD1 | bidirectional | PIO line PA13 shared with FFPI data bit PGMD1. |
| 18 | VDDCORE | power_in | Core, first flash rail, embedded memories and peripherals supply, 1.08 to 1.32 V. |
| 19 | PA12/PGMD0 | bidirectional | PIO line PA12 shared with FFPI data bit PGMD0. |
| 20 | PA11/PGMM3 | bidirectional | PIO line PA11 shared with FFPI programming mode input PGMM3. |
| 21 | PA10/PGMM2 | bidirectional | PIO line PA10 shared with FFPI programming mode input PGMM2. |
| 22 | PA9/PGMM1 | bidirectional | PIO line PA9 shared with FFPI programming mode input PGMM1. |
| 23 | PA8/XOUT32/PGMM0 | bidirectional | PIO line PA8 shared with 32 kHz crystal output XOUT32 and FFPI programming mode input PGMM0. |
| 24 | PA7/XIN32/PGMNVALID | bidirectional | PIO line PA7 shared with 32 kHz crystal input XIN32 and FFPI data direction output PGMNVALID. |
| 25 | TDI/PB4 | bidirectional | JTAG test data input shared with PIO line PB4; voltage must stay within -0.1 V to VDDIO+0.4 V per errata. |
| 26 | PA6/PGMNOE | bidirectional | PIO line PA6 shared with FFPI programming read input PGMNOE. |
| 27 | PA5/PGMRDY | bidirectional | PIO line PA5 shared with FFPI programming ready output PGMRDY. |
| 28 | PA4/PGMNCMD | bidirectional | PIO line PA4 shared with FFPI programming command input PGMNCMD. |
| 29 | NRST | bidirectional | Active-low microcontroller reset, input/output. |
| 30 | TST | input | Test select; low at power-up gives normal operation, high gives test or FFPI mode, with an internal pull-down of about 15 kΩ. |
| 31 | PA3 | bidirectional | PIO line PA3. |
| 32 | PA2/PGMEN2 | bidirectional | PIO line PA2 shared with FFPI programming enable input PGMEN2. |
| 33 | VDDIO | power_in | Peripheral I/O lines supply, 1.62 to 3.6 V. |
| 34 | GND | power_in | Ground. |
| 35 | PA1/PGMEN1 | bidirectional | PIO line PA1 shared with FFPI programming enable input PGMEN1. |
| 36 | PA0/PGMEN0 | bidirectional | PIO line PA0 shared with FFPI programming enable input PGMEN0. |
| 37 | TDO/TRACESWO/PB5 | output | JTAG test data out or asynchronous trace output TRACESWO (SW-DP only), shared with PIO line PB5. |
| 38 | JTAGSEL | input | Active-high JTAG selection input; a chip reset is required after it changes. |
| 39 | TMS/SWDIO/PB6 | bidirectional | JTAG test mode select or serial wire data I/O, shared with PIO line PB6. |
| 40 | TCK/SWCLK/PB7 | input | JTAG test clock or serial wire clock, shared with PIO line PB7. |
| 41 | VDDCORE | power_in | Core, first flash rail, embedded memories and peripherals supply, 1.08 to 1.32 V. |
| 42 | ERASE/PB12 | bidirectional | Flash erase input shared with PIO line PB12. |
| 43 | DDM/PB10 | bidirectional | USB full-speed data minus shared with PIO line PB10. |
| 44 | DDP/PB11 | bidirectional | USB full-speed data plus shared with PIO line PB11. |
| 45 | XOUT/PB8 | bidirectional | 3 to 20 MHz oscillator output shared with PIO line PB8. |
| 46 | XIN/PB9/PGMCK | bidirectional | 3 to 20 MHz oscillator input shared with PIO line PB9 and FFPI programming clock PGMCK. |
| 47 | VDDIO | power_in | Peripheral I/O lines supply, 1.62 to 3.6 V. |
| 48 | VDDPLL | power_in | Supply for PLLA, PLLB, fast RC and 3 to 20 MHz oscillator, 1.08 to 1.32 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range (ATSAM4S4AA-MU, MRL A, Industrial) | | -40 | | 85 | °C | Industrial (-40°C to +85°C) | 1221 |
| VDDIO supply voltage | VDDIO | 1.62 | | 3.6 | V | Powers peripheral I/O lines, USB transceiver, backup part, 32 kHz oscillator | 27 |
| VDDIN supply voltage | VDDIN | 1.62 | | 3.6 | V | Voltage regulator input, ADC, DAC and analog comparator supply | 27 |
| VDDCORE supply voltage | VDDCORE | 1.08 | | 1.32 | V | Powers core, first flash rail, embedded memories and peripherals | 27 |
| VDDPLL supply voltage | VDDPLL | 1.08 | | 1.32 | V | Powers PLLA, PLLB, fast RC and 3 to 20 MHz oscillator | 27 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | before performing the calculation, making the base address for the calculation word-aligned. ̶ Note: To generate the address of an instruction, the constant based on the value of the PC must be | 118 |
## CAD (KiCad official)
- Symbol: `ATSAM4S4AA-MU`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `atsam4s4aa-mu-etched.step` / `atsam4s4aa-mu-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atsam4s4aa-mu.step` / `atsam4s4aa-mu.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/atsam4s4aa-mu-datasheet.pdf) (1269 pp, sha256 `64941c58dfa3899c`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/atsam4s4aa-mu-datasheet.pdf)