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ATSAM4S2BA-AUR

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleratsam4s2ba-aurfactory-2.0.0extractor-text

Verified ATSAM4S2BA-AUR

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAM4S2BA-AUR · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 1269-page datasheet
  • ✓distributor: lcsc C2053847, digikey ATSAM4S2BA-AUR-TR-ND, mouser 556-ATSAM4S2BA-AUR
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_a_1fqp_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.1208)
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 74 kB, viewers/symbol.html 42 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atsam4s2ba-aur.kicad_sym✓ atsam4s2ba-aur.kicad_mod✓ atsam4s2ba-aur.step
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ATSAM4S2BA-AUR

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

ATSAM4S2BA-AUR from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADVREF passive Reference voltage input shared by the ADC, DAC and analog comparator.
2 GND power_in Ground pin.
3 PB0/AD4 bidirectional PIOB line 0, multiplexed with ADC analog input AD4 and RTCOUT0 (Table 42-3).
4 PB1/AD5 bidirectional PIOB line 1, multiplexed with ADC analog input AD5 and RTCOUT1 (Table 42-3).
5 PB2/AD6 bidirectional PIOB line 2, multiplexed with ADC analog input AD6 and wake-up input WKUP12 (Table 42-3).
6 PB3/AD7 bidirectional PIOB line 3, multiplexed with ADC analog input AD7 (Table 42-3).
7 VDDIN power_in Voltage regulator input and supply for the ADC, DAC and analog comparator, 1.62 V to 3.6 V.
8 VDDOUT power_out Output of the internal voltage regulator; its output voltage and capacitor requirements are not given in the extracted text.
9 PA17/PGMD5/AD0 bidirectional PIOA line 17, multiplexed with FFPI programming data PGMD5 and ADC analog input AD0.
10 PA18/PGMD6/AD1 bidirectional PIOA line 18, multiplexed with FFPI programming data PGMD6 and ADC analog input AD1.
11 PA21/PGMD9/AD8 bidirectional PIOA line 21, multiplexed with FFPI programming data PGMD9 and ADC analog input AD8.
12 VDDCORE power_in Core supply powering the core, the first Flash rail and the embedded memories and peripherals, 1.08 V to 1.32 V.
13 PA19/PGMD7/AD2 bidirectional PIOA line 19, multiplexed with FFPI programming data PGMD7 and ADC analog input AD2 (WKUP9).
14 PA22/PGMD10/AD9 bidirectional PIOA line 22, multiplexed with FFPI programming data PGMD10 and ADC analog input AD9.
15 PA23/PGMD11 bidirectional PIOA line 23, multiplexed with FFPI programming data PGMD11.
16 PA20/PGMD8/AD3 bidirectional PIOA line 20, multiplexed with FFPI programming data PGMD8 and ADC analog input AD3 (WKUP10).
17 GND power_in Ground pin.
18 VDDIO power_in Supply for the peripheral I/O lines, USB transceiver, backup part and 32 kHz oscillator, 1.62 V to 3.6 V.
19 PA16/PGMD4 bidirectional PIOA line 16, multiplexed with FFPI programming data PGMD4.
20 PA15/PGMD3 bidirectional PIOA line 15, multiplexed with FFPI programming data PGMD3.
21 PA14/PGMD2 bidirectional PIOA line 14, multiplexed with FFPI programming data PGMD2 and SPI SPCK on peripheral A (Table 33-2).
22 PA13/PGMD1 bidirectional PIOA line 13, multiplexed with FFPI programming data PGMD1 and SPI MOSI on peripheral A (Table 33-2).
23 PA24/PGMD12 bidirectional PIOA line 24, multiplexed with FFPI programming data PGMD12.
24 VDDCORE power_in Core supply powering the core, the first Flash rail and the embedded memories and peripherals, 1.08 V to 1.32 V.
25 PA25/PGMD13 bidirectional PIOA line 25, multiplexed with FFPI programming data PGMD13.
26 PA26/PGMD14 bidirectional PIOA line 26, multiplexed with FFPI programming data PGMD14 and HSMCI MCDA2 on peripheral C (Table 38-2).
27 PA12/PGMD0 bidirectional PIOA line 12, multiplexed with FFPI programming data PGMD0 and SPI MISO on peripheral A (Table 33-2).
28 PA11/PGMM3 bidirectional PIOA line 11, multiplexed with FFPI programming mode input PGMM3 and SPI NPCS0 on peripheral A (Table 33-2).
29 PA10/PGMM2 bidirectional PIOA line 10, multiplexed with FFPI programming mode input PGMM2 and UART0 UTXD0 on peripheral A (Table 35-2).
30 PA9/PGMM1 bidirectional PIOA line 9, multiplexed with FFPI programming mode input PGMM1 and UART0 URXD0 on peripheral A (Table 35-2).
31 PA8/XOUT32/PGMM0 bidirectional PIOA line 8, multiplexed with the 32 kHz crystal oscillator output XOUT32 and FFPI programming mode input PGMM0.
32 PA7/XIN32/PGMNVALID bidirectional PIOA line 7, multiplexed with the 32 kHz crystal oscillator input XIN32 and the FFPI data direction output PGMNVALID.
33 TDI/PB4 bidirectional JTAG test data input TDI, multiplexed with PIOB line 4; per the errata its input low level minimum is 0 V.
34 PA6/PGMNOE bidirectional PIOA line 6, multiplexed with the FFPI programming read input PGMNOE (active low).
35 PA5/PGMRDY bidirectional PIOA line 5, multiplexed with the FFPI programming ready output PGMRDY (active high).
36 PA4/PGMNCMD bidirectional PIOA line 4, multiplexed with the FFPI programming command input PGMNCMD (active low).
37 PA27/PGMD15 bidirectional PIOA line 27, multiplexed with FFPI programming data PGMD15 and HSMCI MCDA3 on peripheral C (Table 38-2).
38 PA28 bidirectional PIOA line 28, general-purpose I/O that also carries TC0 TCLK1 on peripheral B and HSMCI MCCDA on peripheral C.
39 NRST bidirectional Microcontroller reset, active low, configured as an input/output.
40 TST input Test select pin; low at power-up selects normal operation and high selects test or FFPI mode, with an integrated pull-down of about 15 kΩ.
41 PA29 bidirectional PIOA line 29, multiplexed with TC0 TCLK2 on peripheral B and HSMCI MCCK on peripheral C (Tables 37-4, 38-2).
42 PA30 bidirectional PIOA line 30, multiplexed with HSMCI MCDA0 on peripheral C and SPI NPCS2 on peripheral B (Tables 33-2, 38-2).
43 PA3 bidirectional PIOA line 3, multiplexed with SPI NPCS3 on peripheral B (Table 33-2).
44 PA2/PGMEN2 bidirectional PIOA line 2, multiplexed with FFPI programming enable input PGMEN2.
45 VDDIO power_in Supply for the peripheral I/O lines, USB transceiver, backup part and 32 kHz oscillator, 1.62 V to 3.6 V.
46 GND power_in Ground pin.
47 PA1/PGMEN1 bidirectional PIOA line 1, multiplexed with FFPI programming enable input PGMEN1.
48 PA0/PGMEN0 bidirectional PIOA line 0, multiplexed with FFPI programming enable input PGMEN0.
49 TDO/TRACESWO/PB5 bidirectional JTAG test data output TDO, multiplexed with SWD asynchronous trace output TRACESWO and PIOB line 5; when not in debug mode the pin is an input and its pull-up must be enabled to avoid floating-input current.
50 JTAGSEL input Active-high JTAG selection input; it must be high at power-up for boundary scan, and low selects SW-DP or JTAG-DP debug.
51 TMS/SWDIO/PB6 bidirectional JTAG test mode select TMS, SWD bidirectional data SWDIO, multiplexed with PIOB line 6.
52 PA31 bidirectional PIOA line 31, multiplexed with HSMCI MCDA1 on peripheral C and SPI NPCS1 on peripheral A (Tables 33-2, 38-2).
53 TCK/SWCLK/PB7 bidirectional JTAG test clock TCK, SWD clock SWCLK, multiplexed with PIOB line 7.
54 VDDCORE power_in Core supply powering the core, the first Flash rail and the embedded memories and peripherals, 1.08 V to 1.32 V.
55 ERASE/PB12 bidirectional ERASE pin multiplexed with PIOB line 12; the erase behavior is defined in Section 6.5, which is not in the extracted text.
56 DDM/PB10 bidirectional USB Full Speed data minus, multiplexed with PIOB line 10; it resets in USB mode with an internal pull-down.
57 DDP/PB11 bidirectional USB Full Speed data plus, multiplexed with PIOB line 11.
58 VDDIO power_in Supply for the peripheral I/O lines, USB transceiver, backup part and 32 kHz oscillator, 1.62 V to 3.6 V.
59 PB13/DAC0 bidirectional PIOB line 13, multiplexed with the 12-bit DAC analog output DAC0.
60 GND power_in Ground pin.
61 XOUT/PB8 bidirectional Output of the 3 to 20 MHz crystal oscillator, multiplexed with PIOB line 8.
62 XIN/PGMCK/PB9 bidirectional Input of the 3 to 20 MHz crystal oscillator, multiplexed with FFPI programming clock PGMCK and PIOB line 9.
63 PB14/DAC1 bidirectional PIOB line 14, multiplexed with the 12-bit DAC analog output DAC1.
64 VDDPLL power_in Supply for PLLA, PLLB, the fast RC oscillator and the 3 to 20 MHz oscillator, 1.08 V to 1.32 V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Core power supply (VDDCORE) voltage range VDDCORE 1.08 1.32 V 27
I/O power supply (VDDIO) voltage range VDDIO 1.62 3.6 V 27
VDDIO minimum for USB operation VDDIO 3 V For USB, VDDIO needs to be greater than 3.0V 29
Voltage regulator input / ADC-DAC-ACC supply (VDDIN) voltage range VDDIN 1.62 3.6 V 27
VDDIN minimum for ADC, DAC and analog comparator VDDIN 2.4 V For ADC, DAC and Analog Comparator, VDDIN needs to be greater than 2.4V 29
PLL / fast RC / 3-20 MHz oscillator supply (VDDPLL) voltage range VDDPLL 1.08 1.32 V 27
VDDIO rising slope when VDDCORE rises together with VDDIO 8.8 V/ms VDDCORE rising at the same time as VDDIO 27
Voltage regulator static current, Normal mode 500 µA Internal voltage regulator, Normal mode, static current 28
Voltage regulator output current, Normal mode 80 mA Internal voltage regulator, Normal mode 28
Voltage regulator quiescent current, Wait mode 5 µA Internal voltage regulator, Wait mode 28
Voltage regulator current consumption, Backup mode 1 µA Internal voltage regulator in Backup mode 28
Voltage regulator default output voltage VDDOUT 1.2 V Default output voltage 28
Voltage regulator start-up time to Normal mode 300 µs Start-up time to reach Normal mode 28
VDDIO supply monitor threshold range 1.6 3.4 V VDDIO supply monitor, programmable threshold in 16 steps 49
Low-power RC slow clock oscillator frequency 22 42 kHz Low-power RC oscillator selected as slow clock source 328
Maximum operating speed (Cortex-M4 core) 120 MHz 1
Minimum frequency for Flash write commands 330 kHz Write commands of the Flash cannot be used under this frequency 42
HSMCI (MCK/2) pad maximum frequency 70 MHz High-speed pads, HSMCI (MCK/2) 35
SPI clock pad maximum frequency 70 MHz High-speed pads, SPI clock lines 35
Other I/O lines pad maximum frequency 46 MHz High-speed pads, other lines 35
NRST internal pull-up resistor 100 kΩ Permanent pull-up to VDDIO, about 100 kΩ 36
ERASE pin internal pull-down resistor 100 kΩ Permanent pull-down to GND, about 100 kΩ 37
TST pin internal pull-down resistor 15 kΩ Permanent pull-down to GND, about 15 kΩ 37
JTAGSEL internal pull-down resistor 15 kΩ Permanent pull-down to GND, about 15 kΩ 36
Typical I/O pull-up and pull-down resistor 100 kΩ Typical pull-up and pull-down value for all I/Os 35
On-die termination (ODT) series resistance 36 Ω Typical value, on-die termination 35

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC before performing the calculation, making the base address for the calculation word-aligned. ̶ Note: To generate the address of an instruction, the constant based on the value of the PC must be 118

CAD (KiCad official)

  • Symbol: ATSAM4S2BA-AUR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: atsam4s2ba-aur-etched.step / atsam4s2ba-aur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam4s2ba-aur.step / atsam4s2ba-aur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1269 pp, sha256 81933a4a6178f5b3, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF