# ATSAM4LS8CA-AU

**Microchip Tech** · Pre-ordered MCUs · TQFP-100(14x14)

ATSAM4LS8CA-AU from Microchip Tech, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC00 | bidirectional | General-purpose I/O line PC00; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 2 | PC01 | bidirectional | General-purpose I/O line PC01; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 3 | PC02 | bidirectional | General-purpose I/O line PC02; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 4 | PC03 | bidirectional | General-purpose I/O line PC03; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 5 | PA00 | bidirectional | GPIO PA00 on the VDDIO supply domain; also the XIN0 main-oscillator input per Table 3-7. |
| 6 | PA01 | bidirectional | GPIO PA01 on the VDDIO supply domain; also the XOUT0 main-oscillator output per Table 3-7. |
| 7 | GND | power_in | Ground reference pin of the device. |
| 8 | VDDIO | power_in | I/O supply pin for the VDDIO GPIO domain; voltage limits are in Section 9, which is not in the excerpt. |
| 9 | PC04 | bidirectional | General-purpose I/O line PC04; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 10 | PC05 | bidirectional | General-purpose I/O line PC05; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 11 | PC06 | bidirectional | General-purpose I/O line PC06; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 12 | PA02 | bidirectional | GPIO PA02 on the VDDIN supply; multiplexed as SCIF GCLK0, SPI NPCS0 and CATB DIS. |
| 13 | RESET_N | input | External reset pin RESET_N, monitored by the JTAG-FILTER of the Enhanced Debug Port. |
| 14 | VDDCORE | power_out | Core supply pin (VDDCORE); decoupling and regulator requirements are in Section 6, which is not in the excerpt. |
| 15 | GND | power_in | Ground reference pin of the device. |
| 16 | VDDOUT | power_out | Output pin of the embedded voltage regulator (VDDOUT); limits are in Section 6, which is not in the excerpt. |
| 17 | VDDIN | power_in | Supply input pin (VDDIN) for the embedded regulator and the VDDIN GPIO domain; limits are in Section 9, which is not in the excerpt. |
| 18 | TCK | input | JTAG/SW debug clock input (TCK/SWCLK) of the Enhanced Debug Port. |
| 19 | PA03 | bidirectional | GPIO PA03 on the VDDIN supply; multiplexed as SPI MISO and also the JTAG TMS/SWDIO debug pin per Table 3-6. |
| 20 | PB00 | bidirectional | General-purpose I/O line PB00; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 21 | PB01 | bidirectional | General-purpose I/O line PB01; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 22 | PB02 | bidirectional | General-purpose I/O line PB02; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 23 | PB03 | bidirectional | General-purpose I/O line PB03; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 24 | PA04 | bidirectional | GPIO PA04 on the VDDANA supply; multiplexed as ADCIFE AD0, USART0 CLK, EIC EXTINT2, GLOC IN1 and CATB SENSE0. |
| 25 | PA05 | bidirectional | GPIO PA05 on the VDDANA supply; multiplexed as ADCIFE AD1, USART0 RXD, EIC EXTINT3, GLOC IN2, ADCIFE TRIGGER and CATB SENSE1. |
| 26 | XIN32 | input | 32 kHz crystal oscillator input (XIN32), an analog/digital pin per Table 3-8. |
| 27 | XOUT32 | output | 32 kHz crystal oscillator output (XOUT32), an analog pin per Table 3-8. |
| 28 | PB04 | bidirectional | General-purpose I/O line PB04; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 29 | PB05 | bidirectional | General-purpose I/O line PB05; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 30 | PA06 | bidirectional | GPIO PA06 on the VDDANA supply; multiplexed as DACC VOUT, USART0 RTS, EIC EXTINT1, GLOC IN0, ACIFC ACAN0 and CATB SENSE2. |
| 31 | PA07 | bidirectional | GPIO PA07 on the VDDANA supply; multiplexed as ADCIFE AD2, USART0 TXD, EIC EXTINT4, GLOC IN3, ACIFC ACAP0 and CATB SENSE3. |
| 32 | ADVREFN | passive | ADC negative voltage reference pin (ADVREFN); the excerpt gives no further function or limits for it. |
| 33 | GNDANA | power_in | Analog ground pin for the ADC and analog blocks. |
| 34 | ADVREFP | passive | ADC positive voltage reference pin for the ADC controller (ADCIFE), listed as an analog positive voltage reference in Table 3-8. |
| 35 | VDDANA | power_in | Analog supply pin for the VDDANA domain (ADC, DAC and comparator pins such as PA04-PA07); limits are in Section 9, not in the excerpt. |
| 36 | PC07 | bidirectional | General-purpose I/O line PC07; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 37 | PC08 | bidirectional | General-purpose I/O line PC08; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 38 | PC09 | bidirectional | General-purpose I/O line PC09; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 39 | PC10 | bidirectional | General-purpose I/O line PC10; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 40 | PC11 | bidirectional | General-purpose I/O line PC11; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 41 | PC12 | bidirectional | General-purpose I/O line PC12; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 42 | PC13 | bidirectional | General-purpose I/O line PC13; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 43 | PC14 | bidirectional | General-purpose I/O line PC14; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 44 | PA08 | bidirectional | GPIO PA08 on the LCDA supply; multiplexed as USART0 RTS, TC0 A0, PEVC PAD EVT0, GLOC OUT0, LCDCA SEG23 and CATB SENSE4. |
| 45 | PB06 | bidirectional | General-purpose I/O line PB06; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 46 | PB07 | bidirectional | General-purpose I/O line PB07; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 47 | PA09 | bidirectional | GPIO PA09 on the LCDA supply; multiplexed as USART0 CTS, TC0 B0, PEVC PAD EVT1, PARC PCDATA0, LCDCA COM3 and CATB SENSE5. |
| 48 | PA10 | bidirectional | GPIO PA10 on the LCDA supply; multiplexed as USART0 CLK, TC0 A1, PEVC PAD EVT2, PARC PCDATA1, LCDCA COM2 and CATB SENSE6. |
| 49 | PA11 | bidirectional | GPIO PA11 on the LCDA supply; multiplexed as USART0 RXD, TC0 B1, PEVC PAD EVT3, PARC PCDATA2, LCDCA COM1 and CATB SENSE7. |
| 50 | PA12 | bidirectional | GPIO PA12 on the LCDA supply; multiplexed as USART0 TXD, TC0 A2, PARC PCDATA3, LCDCA COM0 and CATB DIS. |
| 51 | PA27 | bidirectional | GPIO PA27 on the LCDA supply; multiplexed as SPI MISO, IISC ISCK, ABDACB DAC0, GLOC IN4, USART3 RTS and CATB SENSE0. |
| 52 | PA28 | bidirectional | GPIO PA28 on the LCDA supply; multiplexed as SPI MOSI, IISC ISDI, ABDACB DACN0, GLOC IN5, USART3 CTS and CATB SENSE1. |
| 53 | PA29 | bidirectional | GPIO PA29 on the LCDA supply; multiplexed as SPI SCK, IISC IWS, ABDACB DAC1, GLOC IN6, USART3 CLK and CATB SENSE2. |
| 54 | GND | power_in | Ground reference pin of the device. |
| 55 | VDDIO | power_in | I/O supply pin for the VDDIO GPIO domain; voltage limits are in Section 9, which is not in the excerpt. |
| 56 | PA30 | bidirectional | GPIO PA30 on the LCDA supply; multiplexed as SPI NPCS0, IISC ISDO, ABDACB DACN1, GLOC IN7, USART3 RXD and CATB SENSE3. |
| 57 | PA31 | bidirectional | GPIO PA31 on the LCDA supply; multiplexed as SPI NPCS1, IISC IMCK, ABDACB CLK, GLOC OUT1, USART3 TXD and CATB DIS. |
| 58 | PC15 | bidirectional | General-purpose I/O line PC15; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 59 | PC16 | bidirectional | General-purpose I/O line PC16; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 60 | PC17 | bidirectional | General-purpose I/O line PC17; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 61 | PC18 | bidirectional | General-purpose I/O line PC18; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 62 | PC19 | bidirectional | General-purpose I/O line PC19; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 63 | PA13 | bidirectional | GPIO PA13 on the LCDA supply; multiplexed as USART1 RTS, TC0 B2, SPI NPCS1, PARC PCDATA4, LCDCA SEG5 and CATB SENSE8. |
| 64 | PA14 | bidirectional | GPIO PA14 on the LCDA supply; multiplexed as USART1 CLK, TC0 CLK0, SPI NPCS2, PARC PCDATA5, LCDCA SEG6 and CATB SENSE9. |
| 65 | PA15 | bidirectional | GPIO PA15 on the LCDA supply; multiplexed as USART1 RXD, TC0 CLK1, SPI NPCS3, PARC PCDATA6, LCDCA SEG7 and CATB SENSE10. |
| 66 | PA16 | bidirectional | GPIO PA16 on the LCDA supply; multiplexed as USART1 TXD, TC0 CLK2, EIC EXTINT1, PARC PCDATA7, LCDCA SEG8 and CATB SENSE11. |
| 67 | PA17 | bidirectional | GPIO PA17 on the LCDA supply; multiplexed as USART2 RTS, ABDACB DAC0, EIC EXTINT2, PARC PCCK, LCDCA SEG9 and CATB SENSE12. |
| 68 | PC20 | bidirectional | General-purpose I/O line PC20; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 69 | PC21 | bidirectional | General-purpose I/O line PC21; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 70 | PC22 | bidirectional | General-purpose I/O line PC22; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 71 | PC23 | bidirectional | General-purpose I/O line PC23; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 72 | PB08 | bidirectional | General-purpose I/O line PB08; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 73 | PB09 | bidirectional | General-purpose I/O line PB09; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 74 | PB10 | bidirectional | General-purpose I/O line PB10; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 75 | PB11 | bidirectional | General-purpose I/O line PB11; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 76 | PA18 | bidirectional | GPIO PA18 on the LCDA supply; multiplexed as USART2 CLK, ABDACB DACN0, EIC EXTINT3, PARC PCEN1, LCDCA SEG18 and CATB SENSE13. |
| 77 | PA19 | bidirectional | GPIO PA19 on the LCDA supply; multiplexed as USART2 RXD, ABDACB DAC1, EIC EXTINT4, PARC PCEN2, SCIF GCLK0, LCDCA SEG19 and CATB SENSE14. |
| 78 | PA20 | bidirectional | GPIO PA20 on the LCDA supply; multiplexed as USART2 TXD, ABDACB DACN1, EIC EXTINT5, GLOC IN0, SCIF GCLK1, LCDCA SEG20 and CATB SENSE15. |
| 79 | PC24 | bidirectional | General-purpose I/O line PC24; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 80 | PC25 | bidirectional | General-purpose I/O line PC25; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 81 | PC26 | bidirectional | General-purpose I/O line PC26; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 82 | PC27 | bidirectional | General-purpose I/O line PC27; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 83 | PC28 | bidirectional | General-purpose I/O line PC28; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 84 | PC29 | bidirectional | General-purpose I/O line PC29; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 85 | PC30 | bidirectional | General-purpose I/O line PC30; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 86 | PC31 | bidirectional | General-purpose I/O line PC31; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 87 | VDDIO | power_in | I/O supply pin for the VDDIO GPIO domain; voltage limits are in Section 9, which is not in the excerpt. |
| 88 | VDDIO | power_in | I/O supply pin for the VDDIO GPIO domain; voltage limits are in Section 9, which is not in the excerpt. |
| 89 | PB12 | bidirectional | General-purpose I/O line PB12; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 90 | PB13 | bidirectional | General-purpose I/O line PB13; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 91 | PA21 | bidirectional | GPIO PA21 on the LCDC supply; multiplexed as SPI MISO, USART1 CTS, EIC EXTINT6, GLOC IN1, TWIM2 TWD, LCDCA SEG34 and CATB SENSE16. |
| 92 | PA22 | bidirectional | GPIO PA22 on the LCDC supply; multiplexed as SPI MOSI, USART2 CTS, EIC EXTINT7, GLOC IN2, TWIM2 TWCK, LCDCA SEG35 and CATB SENSE17. |
| 93 | PB14 | bidirectional | General-purpose I/O line PB14; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 94 | PB15 | bidirectional | General-purpose I/O line PB15; its multiplexed functions and supply domain are listed in Table 3-1, which is not fully in the excerpt. |
| 95 | PA23 | bidirectional | GPIO PA23 on the LCDC supply; multiplexed as SPI SCK, TWIMS0 TWD, EIC EXTINT8, GLOC IN3, SCIF GCLK IN0, LCDCA SEG38 and CATB DIS; it is also the JTAG TDO and ITM SWO trace pin per Tables 3-6 and Section 3.2.4. |
| 96 | PA24 | bidirectional | GPIO PA24 on the LCDC supply; multiplexed as SPI NPCS0, TWIMS0 TWCK, GLOC OUT0, SCIF GCLK IN1, LCDCA SEG39 and CATB SENSE18; it is also the JTAG TDI pin per Table 3-6. |
| 97 | VDDIO | power_in | I/O supply pin for the VDDIO GPIO domain; voltage limits are in Section 9, which is not in the excerpt. |
| 98 | PA25 | bidirectional | GPIO PA25 on the VDDIO supply; multiplexed as USBC DM, USART2 RXD and CATB SENSE19. |
| 99 | PA26 | bidirectional | GPIO PA26 on the VDDIO supply; multiplexed as USBC DP, USART2 TXD and CATB SENSE20. |
| 100 | GND | power_in | Ground reference pin of the device. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature |  | -40 |  | 85 | °C |  | 99 |
| Storage temperature |  | -60 |  | 150 | °C |  | 99 |
| Voltage on input pins with respect to ground |  | -0.3 |  |  | V |  | 99 |
| Total DC output current on all I/O pins |  |  |  | 120 | mA | VDDIO | 99 |
| Total DC output current on all I/O pins |  |  |  | 100 | mA | VDDIN | 99 |
| Total DC output current on all I/O pins |  |  |  | 50 | mA | VDDANA | 99 |
| Maximum operating voltage |  |  |  | 3.6 | V | VDDIO, VDDIN | 99 |
| Operating voltage range | VVDDIN, VVDDIO, VVDDANA | 1.68 |  | 3.6 | V | Operating voltage range for VDDIN, VDDIO and VDDANA; all electrical characteristics unless otherwise specified | 99 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 99 |
| Junction temperature | TJ |  |  | 100 | °C |  | 99 |
| Supply voltage (linear mode, PS1) | VVDDIO, VVDDIN, VVDDANA | 1.68 |  |  | V | PS1 (FCPU<=12MHz), linear mode | 99 |
| Supply voltage (linear mode, PS0 and PS2) | VVDDIO, VVDDIN, VVDDANA | 1.8 |  | 3.6 | V | PS0 & PS2 (FCPU>12MHz), linear mode | 99 |
| Supply voltage (switching mode) | VVDDIO, VVDDIN, VVDDANA | 2 |  |  | V | Switching mode | 99 |
| Supply rise rate VDDIO | VVDDIO | 0.0001 |  | 2.5 | V/µs | DC supply peripheral I/Os | 100 |
| Supply rise rate VDDIN | VVDDIN | 0.0001 |  | 2.5 | V/µs | DC supply peripheral I/Os and internal regulator | 100 |
| Supply rise rate VDDANA | VVDDANA | 0.0001 |  | 2.5 | V/µs | Analog supply voltage | 100 |
| CPU clock frequency | fCPU |  |  | 12 | MHz | Power scaling mode 1 and RUN mode | 102 |
| Crystal oscillator frequency (OSC0) | fOUT | 0.6 |  | 30 | MHz |  | 121 |
| RCFAST output frequency | fOUT | 4 | 4.3 | 4.6 | MHz | Calibrated, FRANGE=0 | 126 |
| RCFAST output frequency | fOUT | 7.8 | 8.2 | 8.5 | MHz | Calibrated, FRANGE=1 | 126 |
| RCFAST output frequency | fOUT | 11.3 | 12 | 12.3 | MHz | Calibrated, FRANGE=2 | 126 |
| DFLL output frequency | fOUT | 20 |  | 150 | MHz | DFLL is not available in PS1 | 124 |
| PLL output frequency | fOUT | 48 |  | 240 | MHz | PLL is not available in PS1 | 124 |
| Low-level input voltage | VIL | -0.3 |  |  | V |  | 114 |
| Output low-level voltage | VOL |  |  | 0.4 | V |  | 114 |
| Voltage threshold on VVDDIN rising (POR33) | VPOT+ | 1.25 |  | 1.55 | V |  | 131 |
| Voltage threshold on VVDDIN falling (POR33) | VPOT- | 0.95 |  | 1.3 | V |  | 131 |
| Supply voltage VDDANA | VDDANA | 1.6 |  | 3.6 | V |  | 134 |
| DC output current (WAIT, low power mode) | IOUT | 2000 | 3600 | 5600 | µA | Power scaling mode 0 & 2, Low power mode (WAIT) | 129 |
| DC output current (RETENTION, ultra low power mode) | IOUT | 100 | 180 | 300 | µA | Power scaling mode 0 & 2, Ultra Low power mode (RETENTION) | 129 |
| DC output current (WAIT, low power mode) | IOUT | 4000 | 7000 | 10000 | µA | Power scaling mode 1, Low power mode (WAIT) | 129 |
| DC output current (RETENTION, ultra low power mode) | IOUT | 200 | 350 | 600 | µA | Power scaling mode 1, Ultra Low power mode (RETENTION) | 129 |
| Input voltage range (linear mode) | VVDDIN | 1.68 |  | 3.6 | V | IOUT=10mA | 129 |
| Input voltage range (linear mode) | VVDDIN | 1.8 |  | 3.6 | V | IOUT=50mA | 129 |
| DC output voltage (linear mode) | VVDDCORE | 1.777 | 1.814 | 1.854 | V | Power scaling mode 0 & 2, IOUT = 0 mA | 129 |
| DC output voltage (linear mode) | VVDDCORE | 1.75 | 1.79 | 1.83 | V | Power scaling mode 0 & 2, IOUT = 50 mA | 129 |
| DC output current (linear mode) | IOUT |  |  | 100 | mA | VVDDCORE > 1.65V | 129 |
| Input voltage range (switching mode) | VVDDIN | 2 |  | 3.6 | V | VVDDCORE = 1.65V, IOUT=50mA | 129 |
| DC output voltage (switching mode) | VVDDCORE | 1.75 | 1.82 | 1.87 | V | Power scaling mode 0 & 2, IOUT = 0 mA | 129 |
| DC output voltage (switching mode) | VVDDCORE | 1.66 | 1.71 | 1.79 | V | Power scaling mode 0 & 2, IOUT = 50 mA | 129 |
| DC output current (switching mode) | IOUT |  |  | 55 | mA | VVDDCORE > 1.65V | 130 |
| RUN current, CPU running Fibonacci algorithm, linear mode |  |  | 319 | 343 | µA/MHz | TA=25°C, linear mode | 104 |
| RUN current, CPU running Fibonacci algorithm, linear mode |  |  | 326 | 350 | µA/MHz | TA=85°C, linear mode | 104 |
| RUN current, CPU running CoreMark algorithm, linear mode |  |  | 343 | 387 | µA/MHz | TA=25°C, linear mode | 104 |
| RUN current, CPU running CoreMark algorithm, linear mode |  |  | 351 | 416 | µA/MHz | TA=85°C, linear mode | 104 |
| RUN current, CPU running Fibonacci algorithm, switching mode |  |  | 181 | 198 | µA/MHz | TA=25°C, switching mode | 104 |
| RUN current, CPU running Fibonacci algorithm, switching mode |  |  | 186 | 203 | µA/MHz | TA=85°C, switching mode | 104 |
| RUN current, CPU running CoreMark algorithm, switching mode |  |  | 192 | 232 | µA/MHz | TA=25°C, switching mode | 104 |
| RUN current, CPU running CoreMark algorithm, switching mode |  |  | 202 | 239 | µA/MHz | TA=85°C, switching mode | 104 |
| SLEEP0 current |  |  | 3817 | 4033 | µA | TA=25°C, switching mode | 105 |
| SLEEP0 current |  |  | 4050 | 4507 | µA | TA=85°C, switching mode | 105 |
| SLEEP1 current |  |  | 2341 | 2477 | µA | TA=25°C, switching mode | 105 |
| SLEEP1 current |  |  | 2525 | 2832 | µA | TA=85°C, switching mode | 105 |
| SLEEP2 current |  |  | 1758 | 1862 | µA | TA=25°C, switching mode | 105 |
| SLEEP2 current |  |  | 1925 | 1971 | µA | TA=85°C, switching mode | 105 |
| SLEEP3 current |  |  | 51 | 60 | µA | TA=25°C, linear mode | 105 |
| BACKUP current |  |  | 1.5 | 3.1 | µA | OSC32K running, AST running at 1kHz | 105 |
| BACKUP current |  |  | 0.9 | 1.7 | µA | AST and OSC32K stopped | 105 |
| Junction-to-ambient thermal resistance (TQFP100) | θJA |  | 48.1 |  | °C/W | Still Air | 153 |
| Junction-to-case thermal resistance (TQFP100) | θJC |  | 13.3 |  | °C/W |  | 153 |

## CAD (KiCad official)

- Symbol: `ATSAM4LS8CA-AU`
- Footprint: `Package_QFP:TQFP-100_14x14mm_P0.5mm`
- 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `atsam4ls8ca-au-etched.step` / `atsam4ls8ca-au-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atsam4ls8ca-au.step` / `atsam4ls8ca-au.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/atsam4ls8ca-au-datasheet.pdf) (176 pp, sha256 `de2398a17cf48aca`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/atsam4ls8ca-au-datasheet.pdf)