ATSAM4LC8CA-AU from Microchip Tech, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC00	bidirectional	GPIO line PC00; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
2	PC01	bidirectional	GPIO line PC01; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
3	PC02	bidirectional	GPIO line PC02; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
4	PC03	bidirectional	GPIO line PC03; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
5	PA00	bidirectional	GPIO line PA00 supplied from VDDIO; per Table 3-7 it is also the XIN0 oscillator input pin.
6	PA01	bidirectional	GPIO line PA01 supplied from VDDIO; per Table 3-7 it is also the XOUT0 oscillator output pin.
7	GND	power_in	Ground pin.
8	VDDIO	power_in	I/O supply pin for the GPIO ring.
9	PC04	bidirectional	GPIO line PC04; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
10	PC05	bidirectional	GPIO line PC05; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
11	PC06	bidirectional	GPIO line PC06; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
12	PA02	bidirectional	GPIO line PA02 supplied from VDDIN, multiplexed with SCIF GCLK0, SPI NPCS0 and CATB DIS per Table 3-1.
13	RESET_N	input	External active-low reset input.
14	VDDCORE	power_in	Core supply pin; the power and startup section describes its connection to the regulator.
15	GND	power_in	Ground pin.
16	VDDOUT	power_out	Output of the embedded voltage regulator.
17	VDDIN	power_in	Supply input pin for the embedded regulator and the VDDIN-supplied GPIO lines.
18	TCK	input	JTAG/SWD debug clock input, per Table 3-6 and the Enhanced Debug Port description.
19	PA03	bidirectional	GPIO line PA03 supplied from VDDIN, multiplexed with SPI MISO per Table 3-1 and JTAG TMS per Table 3-6.
20	PB00	bidirectional	GPIO line PB00; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
21	PB01	bidirectional	GPIO line PB01; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
22	PB02	bidirectional	GPIO line PB02; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
23	PB03	bidirectional	GPIO line PB03; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
24	PA04	bidirectional	GPIO line PA04 supplied from VDDANA, multiplexed with ADCIFE AD0, USART0 CLK, EIC EXTINT2, GLOC IN1 and CATB SENSE0 per Table 3-1.
25	PA05	bidirectional	GPIO line PA05 supplied from VDDANA, multiplexed with ADCIFE AD1, USART0 RXD, EIC EXTINT3, GLOC IN2, ADCIFE TRIGGER and CATB SENSE1 per Table 3-1.
26	XIN32	input	32 kHz crystal oscillator input.
27	XOUT32	output	32 kHz crystal oscillator output.
28	PB04	bidirectional	GPIO line PB04; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
29	PB05	bidirectional	GPIO line PB05; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
30	PA06	bidirectional	GPIO line PA06 supplied from VDDANA, multiplexed with DACC VOUT, USART0 RTS, EIC EXTINT1, GLOC IN0, ACIFC ACAN0 and CATB SENSE2 per Table 3-1.
31	PA07	bidirectional	GPIO line PA07 supplied from VDDANA, multiplexed with ADCIFE AD2, USART0 TXD, EIC EXTINT4, GLOC IN3, ACIFC ACAP0 and CATB SENSE3 per Table 3-1.
32	ADVREFN	passive	ADC negative voltage reference pin.
33	GNDANA	power_in	Analog ground pin.
34	ADVREFP	passive	ADC positive voltage reference pin; the signal description lists ADVREFP as the positive voltage reference.
35	VDDANA	power_in	Analog supply pin.
36	PC07	bidirectional	GPIO line PC07; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
37	PC08	bidirectional	GPIO line PC08; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
38	PC09	bidirectional	GPIO line PC09; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
39	PC10	bidirectional	GPIO line PC10; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
40	PC11	bidirectional	GPIO line PC11; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
41	PC12	bidirectional	GPIO line PC12; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
42	PC13	bidirectional	GPIO line PC13; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
43	PC14	bidirectional	GPIO line PC14; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
44	PA08	bidirectional	GPIO line PA08 supplied from LCDA, multiplexed with USART0 RTS, TC0 A0, PEVC PAD EVT0, GLOC OUT0, LCDCA SEG23 and CATB SENSE4 per Table 3-1.
45	PB06	bidirectional	GPIO line PB06; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
46	PB07	bidirectional	GPIO line PB07; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
47	PA09	bidirectional	GPIO line PA09 supplied from LCDA, multiplexed with USART0 CTS, TC0 B0, PEVC PAD EVT1, PARC PCDATA0, LCDCA COM3 and CATB SENSE5 per Table 3-1.
48	PA10	bidirectional	GPIO line PA10 supplied from LCDA, multiplexed with USART0 CLK, TC0 A1, PEVC PAD EVT2, PARC PCDATA1, LCDCA COM2 and CATB SENSE6 per Table 3-1.
49	PA11	bidirectional	GPIO line PA11 supplied from LCDA, multiplexed with USART0 RXD, TC0 B1, PEVC PAD EVT3, PARC PCDATA2, LCDCA COM1 and CATB SENSE7 per Table 3-1.
50	PA12	bidirectional	GPIO line PA12 supplied from LCDA, multiplexed with USART0 TXD, TC0 A2, PARC PCDATA3, LCDCA COM0 and CATB DIS per Table 3-1.
51	CAPH	passive	LCD controller capacitor connection (CAPH).
52	CAPL	passive	LCD controller capacitor connection (CAPL).
53	VLCD	passive	LCD controller voltage pin (VLCD).
54	BIASH	passive	LCD controller bias pin (BIASH).
55	BIASL	passive	LCD controller bias pin (BIASL).
56	GND	power_in	Ground pin.
57	VLCDIN	power_in	LCD controller supply input (VLCDIN).
58	PC15	bidirectional	GPIO line PC15; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
59	PC16	bidirectional	GPIO line PC16; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
60	PC17	bidirectional	GPIO line PC17; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
61	PC18	bidirectional	GPIO line PC18; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
62	PC19	bidirectional	GPIO line PC19; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
63	PA13	bidirectional	GPIO line PA13 supplied from LCDA, multiplexed with USART1 RTS, TC0 B2, SPI NPCS1, PARC PCDATA4, LCDCA SEG5 and CATB SENSE8 per Table 3-1.
64	PA14	bidirectional	GPIO line PA14 supplied from LCDA, multiplexed with USART1 CLK, TC0 CLK0, SPI NPCS2, PARC PCDATA5, LCDCA SEG6 and CATB SENSE9 per Table 3-1.
65	PA15	bidirectional	GPIO line PA15 supplied from LCDA, multiplexed with USART1 RXD, TC0 CLK1, SPI NPCS3, PARC PCDATA6, LCDCA SEG7 and CATB SENSE10 per Table 3-1.
66	PA16	bidirectional	GPIO line PA16; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
67	PA17	bidirectional	GPIO line PA17; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
68	PC20	bidirectional	GPIO line PC20; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
69	PC21	bidirectional	GPIO line PC21; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
70	PC22	bidirectional	GPIO line PC22; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
71	PC23	bidirectional	GPIO line PC23; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
72	PB08	bidirectional	GPIO line PB08; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
73	PB09	bidirectional	GPIO line PB09; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
74	PB10	bidirectional	GPIO line PB10; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
75	PB11	bidirectional	GPIO line PB11; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
76	PA18	bidirectional	GPIO line PA18; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
77	PA19	bidirectional	GPIO line PA19; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
78	PA20	bidirectional	GPIO line PA20; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
79	PC24	bidirectional	GPIO line PC24; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
80	PC25	bidirectional	GPIO line PC25; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
81	PC26	bidirectional	GPIO line PC26; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
82	PC27	bidirectional	GPIO line PC27; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
83	PC28	bidirectional	GPIO line PC28; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
84	PC29	bidirectional	GPIO line PC29; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
85	PC30	bidirectional	GPIO line PC30; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
86	PC31	bidirectional	GPIO line PC31; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
87	VDDIO	power_in	I/O supply pin for the GPIO ring.
88	VDDIO	power_in	I/O supply pin for the GPIO ring.
89	PB12	bidirectional	GPIO line PB12; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
90	PB13	bidirectional	GPIO line PB13; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
91	PA21	bidirectional	GPIO line PA21; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
92	PA22	bidirectional	GPIO line PA22; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
93	PB14	bidirectional	GPIO line PB14; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
94	PB15	bidirectional	GPIO line PB15; its supply domain and peripheral multiplexing are in the Section 3.2 tables, which are not in this excerpt.
95	PA23	bidirectional	GPIO line PA23; per Table 3-6 it is a JTAG TDO pin, and per Section 3.2.4 it carries the Serial Wire Trace signal when ITM trace is enabled.
96	PA24	bidirectional	GPIO line PA24; per Table 3-6 it is a JTAG TDI pin.
97	VDDIO	power_in	I/O supply pin for the GPIO ring.
98	PA25	bidirectional	GPIO line PA25; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
99	PA26	bidirectional	GPIO line PA26; its peripheral multiplexing is in the Section 3.2 tables, which are not in this excerpt.
100	GND	power_in	Ground pin.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	TQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating voltage range VDDIN, VDDIO, VDDANA	VVDDIN, VVDDIO, VVDDANA	1.68		3.6	V	Operating voltage range for VDDIN, VDDIO & VDDANA	99
Operating temperature range	TA	-40		85	°C		99
Junction temperature	TJ			100	°C	Junction temperature up to TJ = 100°C	99
Operating temperature		-40		85	°C		99
Storage temperature		-60		150	°C		99
Voltage on input pins with respect to ground		-0.3			V	Maximum printed as VVDD + 0.3 V (VVDD = VVDDIN or VVDDIO)	99
Total DC output current on all I/O pins, VDDIO				120	mA		99
Total DC output current on all I/O pins, VDDIN				100	mA		99
Total DC output current on all I/O pins, VDDANA				50	mA		99
Maximum operating voltage VDDIO, VDDIN				3.6	V		99
DC supply rise rate, peripheral I/Os	VVDDIO	0.0001		2.5	V/µs		100
DC supply rise rate, peripheral I/Os and internal regulator	VVDDIN	0.0001		2.5	V/µs		100
Analog supply voltage rise rate	VVDDANA	0.0001		2.5	V/µs		100
RUN current, CPU running Fibonacci algorithm			319	343	µA/MHz	Linear mode, TA=25°C	104
RUN current, CPU running Fibonacci algorithm			326	350	µA/MHz	Linear mode, TA=85°C	104
RUN current, CPU running CoreMark algorithm			343	387	µA/MHz	Linear mode, TA=25°C	104
RUN current, CPU running CoreMark algorithm			351	416	µA/MHz	Linear mode, TA=85°C	104
RUN current, CPU running Fibonacci algorithm			181	198	µA/MHz	Switching mode, TA=25°C	104
RUN current, CPU running Fibonacci algorithm			186	203	µA/MHz	Switching mode, TA=85°C	104
RUN current, CPU running CoreMark algorithm			192	232	µA/MHz	Switching mode, TA=25°C	104
RUN current, CPU running CoreMark algorithm			202	239	µA/MHz	Switching mode, TA=85°C	104
SLEEP0 current			3817	4033	µA	Switching mode, TA=25°C	105
SLEEP0 current			4050	4507	µA	Switching mode, TA=85°C	105
SLEEP1 current			2341	2477	µA	Switching mode, TA=25°C	105
SLEEP1 current			2525	2832	µA	Switching mode, TA=85°C	105
SLEEP2 current			1758	1862	µA	Switching mode, TA=25°C	105
SLEEP2 current			1925	1971	µA	Switching mode, TA=85°C	105
SLEEP3 current			51	60	µA	Linear mode, TA=25°C	105
BACKUP current			1.5	3.1	µA	OSC32K running, AST running at 1kHz	105
BACKUP current			0.9	1.7	µA	AST and OSC32K stopped	105
VVDDIN input voltage range	VVDDIN	1.68		3.6	V	IOUT=10mA, linear mode	129
VVDDIN input voltage range	VVDDIN	1.8		3.6	V	IOUT=50mA, linear mode	129
VVDDCORE DC output voltage, linear mode	VVDDCORE	1.777	1.814	1.854	V	Power scaling mode 0 & 2, IOUT = 0 mA	129
VVDDCORE DC output voltage, linear mode	VVDDCORE	1.75	1.79	1.83	V	Power scaling mode 0 & 2, IOUT = 50 mA	129
Quiescent current, linear mode	IQ	88	107	128	µA	IOUT = 0 mA, RUN and SLEEPx modes	129
VVDDIN input voltage range, switching mode	VVDDIN	2		3.6	V	VVDDCORE = 1.65V, IOUT=50mA	129
VVDDCORE DC output voltage, switching mode	VVDDCORE	1.75	1.82	1.87	V	Power scaling mode 0 & 2, IOUT = 0 mA	129
VVDDCORE DC output voltage, switching mode	VVDDCORE	1.66	1.71	1.79	V	Power scaling mode 0 & 2, IOUT = 50 mA	129
Quiescent current, switching mode	IQ	97	186	546	µA	VVDDIN = 2V, IOUT = 0 mA	130
Quiescent current, switching mode	IQ	97	111	147	µA	VVDDIN > 2.2V, IOUT = 0 mA	130
VDDANA supply voltage	VDDANA	1.6		3.6	V	Supply voltage	134
POR33 voltage threshold, VVDDIN rising	VPOT+	1.25		1.55	V	Voltage threshold on VVDDIN rising	131
POR33 voltage threshold, VVDDIN falling	VPOT-	0.95		1.3	V	Voltage threshold on VVDDIN falling	131
32kHz RC oscillator output frequency	fOUT	20	32.768	44	kHz	Calibrated against a 32.768kHz reference, temperature compensation disabled	125
System RC oscillator output frequency	fOUT	110	113.6	116	kHz	Calibrated at 85°C	125
1MHz RC oscillator output frequency	fOUT	0.91	1	1.12	MHz		126
4/8/12MHz RC oscillator output frequency	fOUT	4	4.3	4.6	MHz	Calibrated, FRANGE=0	126
4/8/12MHz RC oscillator output frequency	fOUT	7.8	8.2	8.5	MHz	Calibrated, FRANGE=1	126
4/8/12MHz RC oscillator output frequency	fOUT	11.3	12	12.3	MHz	Calibrated, FRANGE=2	126
80MHz RC oscillator output frequency	fOUT	60	80	100	MHz	After calibration; RC80M not available in PS1	127
Crystal oscillator frequency	fOUT	0.6		30	MHz		121
Crystal load capacitance	CL	6		18	pF		122
PLL output frequency	fOUT	48		240	MHz	PLL is not available in PS1	124
DFLL output frequency	fOUT	20		150	MHz	DFLL is not available in PS1	124
Normal I/O input low-level voltage	VIL	-0.3			V		114
Junction-to-ambient thermal resistance, TQFP100	θJA		48.1		°C/W	Still air	153
Junction-to-case thermal resistance, TQFP100	θJC		13.3		°C/W		153

CAD (KiCad official)

Symbol: ATSAM4LC8CA-AU
Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: atsam4lc8ca-au-etched.step / atsam4lc8ca-au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam4lc8ca-au.step / atsam4lc8ca-au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (176 pp, sha256 188d7648dafe2946, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ATSAM4LC8CA-AU

Verified ATSAM4LC8CA-AU

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README