component

ATSAM3U1CB-AU

Public Made by Adom

by adom

Microchip Tech Pre-ordered MCUs, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatsam3u1cb-aufactory-2.0.0extractor-text

Verified ATSAM3U1CB-AU

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAM3U1CB-AU · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 1163-page datasheet
  • ✓distributor: lcsc C1337165, digikey ATSAM3U1CB-AU-ND, mouser 556-ATSAM3U1CB-AU
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rs0j7z6e/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atsam3u1cb-au.kicad_sym✓ atsam3u1cb-au.kicad_mod✓ atsam3u1cb-au.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs atsam3u1cb-au: hero re-rendered with the chip (after the 10-30 render outage) · Ray 5d ago
viewers atsam3u1cb-au: viewers · Ray 5d ago
atsam3u1cb-au-etched.glb Publish 0.1.0 · Ray 5d ago
atsam3u1cb-au-etched.step atsam3u1cb-au: factory component page (tier=mfr) · Ray 5d ago
atsam3u1cb-au-hero.glb atsam3u1cb-au: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
atsam3u1cb-au-hero.overlay.json Publish 0.1.0 · Ray 5d ago
atsam3u1cb-au.glb Publish 0.1.0 · Ray 5d ago
atsam3u1cb-au.kicad_mod Publish 0.1.0 · Ray 5d ago
atsam3u1cb-au.kicad_sym Publish 0.1.0 · Ray 5d ago
atsam3u1cb-au.lbr Publish 0.1.0 · Ray 5d ago
atsam3u1cb-au.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 100 pins · Ray 5d ago

ATSAM3U1CB-AU

Microchip Tech · Pre-ordered MCUs · LQFP-100(14x14)

ATSAM3U1CB-AU from Microchip Tech, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDANA power_in Powers the ADC cells; voltage range 2.0-3.6 V.
2 ADVREF input Reference for the 10-bit ADC; conversions extend from 0 V to ADVREF.
3 GNDANA power_in Separate ground for the analog (VDDANA) supply domain.
4 AD12BVREF input Reference for the 12-bit ADC (ADC12B); conversions extend from 0 V to AD12BVREF.
5 PA22/PGMD14 bidirectional PIO line PA22 (also PGMD14 in the pin name); listed as an ADC analog input in the errata.
6 PA30 bidirectional PIO line PA30, which is TC0 TIOA2 (peripheral B) and SSC TF (peripheral A); listed as an ADC analog input in the errata.
7 PB3 bidirectional PIO line PB3; listed as an ADC analog input in the errata.
8 PB4 bidirectional PIO line PB4, which is TC0 TCLK1 (peripheral A); listed as an ADC analog input in the errata.
9 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
10 PA13/PGMD5 bidirectional PIO line PA13, which is SPI MISO (peripheral A).
11 PA14/PGMD6 bidirectional PIO line PA14, which is SPI MOSI (peripheral A).
12 PA15/PGMD7 bidirectional PIO line PA15, which is SPI SPCK (peripheral A).
13 PA16/PGMD8 bidirectional PIO line PA16, which is SPI NPCS0 (peripheral A).
14 PA17/PGMD9 bidirectional PIO line PA17; no peripheral function is listed in the provided excerpt.
15 PB16 bidirectional PIO line PB16; no peripheral function is listed in the provided excerpt.
16 PB15 bidirectional PIO line PB15; no peripheral function is listed in the provided excerpt.
17 PA18/PGMD10 bidirectional PIO line PA18; no peripheral function is listed in the provided excerpt.
18 PA19/PGMD11 bidirectional PIO line PA19, which is SPI NPCS3 (peripheral B).
19 PA20/PGMD12 bidirectional PIO line PA20; no peripheral function is listed in the provided excerpt.
20 PA21/PGMD13 bidirectional PIO line PA21; no peripheral function is listed in the provided excerpt.
21 PA23/PGMD15 bidirectional PIO line PA23; no peripheral function is listed in the provided excerpt.
22 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
23 PA24 bidirectional PIO line PA24, which is TWI1 TWD1 (peripheral A).
24 PA25 bidirectional PIO line PA25, which is TWI1 TWCK1 (peripheral A).
25 PA26 bidirectional PIO line PA26, which is SSC TD (peripheral A) and TC0 TCLK2 (peripheral B).
26 PA0/PGMNCMD bidirectional PIO line PA0, which is SPI NPCS1 (peripheral B) and TC0 TIOB0 (peripheral A).
27 PA1/PGMRDY bidirectional PIO line PA1, which is SPI NPCS2 (peripheral B) and TC0 TIOA0 (peripheral A).
28 PA2/PGMNOE bidirectional PIO line PA2, which is TC0 TCLK0 (peripheral A) and ADC12B AD12BTRG (peripheral B).
29 PA3/PGMNVALID bidirectional PIO line PA3, which is HSMCI MCCK (peripheral A).
30 PA4/PGMM0 bidirectional PIO line PA4, which is HSMCI MCCDA (peripheral A).
31 PA5/PGMM1 bidirectional PIO line PA5, which is HSMCI MCDA0 (peripheral A).
32 PA6/PGMM2 bidirectional PIO line PA6, which is HSMCI MCDA1 (peripheral A).
33 PA7/PGMM3 bidirectional PIO line PA7, which is HSMCI MCDA2 (peripheral A).
34 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
35 GND power_in Ground common to the VDDCORE and VDDIO power supplies.
36 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
37 PA8/PGMD0 bidirectional PIO line PA8, which is HSMCI MCDA3 (peripheral A).
38 PA9/PGMD1 bidirectional PIO line PA9, which is TWI0 TWD0 (peripheral A).
39 PA10/PGMD2 bidirectional PIO line PA10, which is TWI0 TWCK0 (peripheral A).
40 PA11/PGMD3 bidirectional PIO line PA11, which is UART URXD (peripheral A).
41 PA12/PGMD4 bidirectional PIO line PA12, which is UART UTXD (peripheral A).
42 FWUP input Fast wake-up pin; boundary scan is enabled when FWUP, NRST, NRSTB and JTAGSEL are high while TST is tied low during power-up.
43 ERASE input ERASE pin related to reprogramming Flash content; detailed behavior is in Section 6.7, which is not in the provided excerpt.
44 TST input Test select: low at power-up selects normal operation and high selects test or FFPI mode; it has an internal pull-down of about 15 kΩ.
45 VDDBU power_in Powers the Slow Clock oscillator and part of the System Controller; voltage range 1.62-3.6 V and must be supplied before or at the same time as VDDIO and VDDCORE.
46 GNDBU power_in Separate ground for the VDDBU backup domain.
47 NRSTB input Reset-related input in the VDDBU domain per the revision history; it must be high, together with FWUP, NRST and JTAGSEL, to enable boundary scan.
48 JTAGSEL input Active-high JTAG select: high enables IEEE 1149.1 boundary scan, low selects SW-DP or JTAG-DP, and a chip reset is required after changing it.
49 XOUT32 output Output of the 32.768 kHz crystal oscillator; leave unconnected if the crystal is not used.
50 XIN32 input Input of the 32.768 kHz crystal oscillator; in bypass mode an external clock is applied here and it should be left unconnected if the oscillator is unused.
51 TDI input JTAG test data input for the SWJ debug port.
52 VDDOUT power_out Output of the internal voltage regulator.
53 VDDIN power_in Powers the internal voltage regulator.
54 TDO/TRACESWO output JTAG test data output, or asynchronous trace output (TRACESWO) in SWD mode; it is an input when not in debug mode, so an external 100 kΩ pull-up is recommended.
55 TMS/SWDIO bidirectional JTAG test mode select, or serial wire data input/output (SWDIO) in SWD mode.
56 TCK/SWCLK input JTAG test clock, or serial wire clock (SWCLK) in SWD mode.
57 NRST bidirectional Microcontroller reset, active low, configured as input/output.
58 PB24 bidirectional PIO line PB24; no peripheral function is listed in the provided excerpt.
59 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
60 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
61 GND power_in Ground common to the VDDCORE and VDDIO power supplies.
62 PB23 bidirectional PIO line PB23; no peripheral function is listed in the provided excerpt.
63 PB22 bidirectional PIO line PB22; no peripheral function is listed in the provided excerpt.
64 PB21 bidirectional PIO line PB21; no peripheral function is listed in the provided excerpt.
65 PB20 bidirectional PIO line PB20; no peripheral function is listed in the provided excerpt.
66 PB19 bidirectional PIO line PB19; no peripheral function is listed in the provided excerpt.
67 PB18 bidirectional PIO line PB18; no peripheral function is listed in the provided excerpt.
68 PB17 bidirectional PIO line PB17; no peripheral function is listed in the provided excerpt.
69 PB14 bidirectional PIO line PB14; no peripheral function is listed in the provided excerpt.
70 PB10 bidirectional PIO line PB10; no peripheral function is listed in the provided excerpt.
71 PB9 bidirectional PIO line PB9; no peripheral function is listed in the provided excerpt.
72 GNDPLL power_in Separate ground for the VDDPLL domain (PLL A, UPLL and 3-20 MHz oscillator).
73 VDDPLL power_in Powers PLL A, UPLL and the 3-20 MHz oscillator; voltage range 1.62-1.95 V.
74 XOUT output Output of the 3-20 MHz crystal oscillator.
75 XIN input Input of the 3-20 MHz crystal oscillator.
76 DHSDP bidirectional Data+ line of the High Speed USB device port with embedded transceiver.
77 DHSDM bidirectional Data- line of the High Speed USB device port with embedded transceiver.
78 VBG passive Bandgap voltage reference pin; no electrical limits are stated in the provided excerpt.
79 VDDUTMI power_in Powers the UTMI+ interface; voltage range 3.0-3.6 V, 3.3 V nominal.
80 DFSDM bidirectional USB device data- line (DFSDM), paired with DFSDP; no electrical limits are given in the provided excerpt.
81 DFSDP bidirectional USB device data+ line (DFSDP), paired with DFSDM; no electrical limits are given in the provided excerpt.
82 GNDUTMI power_in Separate ground for the VDDUTMI domain.
83 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
84 PA28 bidirectional PIO line PA28, which is SSC TK (peripheral A).
85 PA29 bidirectional PIO line PA29, which is SSC RK (peripheral A).
86 PA31 bidirectional PIO line PA31, which is SSC RF (peripheral A) and TC0 TIOB2 (peripheral B).
87 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
88 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
89 GND power_in Ground common to the VDDCORE and VDDIO power supplies.
90 PB0 bidirectional PIO line PB0; no peripheral function is listed in the provided excerpt.
91 PB1 bidirectional PIO line PB1; no peripheral function is listed in the provided excerpt.
92 PB2 bidirectional PIO line PB2; no peripheral function is listed in the provided excerpt.
93 PB11 bidirectional PIO line PB11; no peripheral function is listed in the provided excerpt.
94 PB12 bidirectional PIO line PB12; no peripheral function is listed in the provided excerpt.
95 PB13 bidirectional PIO line PB13; no peripheral function is listed in the provided excerpt.
96 PA27 bidirectional PIO line PA27, which is SSC RD (peripheral A).
97 PB5 bidirectional PIO line PB5, which is TC0 TIOA1 (peripheral A); listed as an ADC analog input in the errata.
98 PB6 bidirectional PIO line PB6, which is TC0 TIOB1 (peripheral A); listed as an ADC analog input in the errata.
99 PB7 bidirectional PIO line PB7; listed as an ADC analog input in the errata.
100 PB8 bidirectional PIO line PB8; listed as an ADC analog input in the errata.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDDCORE supply voltage range VDDCORE 1.62 1.95 V 17
VDDIO supply voltage range (I/O lines) VDDIO 1.62 3.6 V 17
VDDBU supply voltage range (backup, slow clock, part of SUPC) VDDBU 1.62 3.6 V 17
VDDPLL supply voltage range (PLL A, UPLL, 3-20 MHz oscillator) VDDPLL 1.62 1.95 V 17
VDDUTMI supply voltage range (UTMI+ interface) VDDUTMI 3 3.3 3.6 V 17
VDDANA supply voltage range (ADC cells) VDDANA 2 3.6 V 17
Single supply mode operating voltage range 1.62 3.6 V Single supply mode via internal regulator 19
VDDIO minimum operating voltage before VDDCORE reaches its minimum 1.6 V Power-up sequencing 17
VDDIO minimum rising slope 5 V/ms VDDCORE rising at the same time as VDDIO 17
Voltage regulator static current, Normal mode 700 µA Normal mode, static current 17
Voltage regulator output current 150 mA Normal mode 17
Voltage regulator quiescent current in Wait mode or low output current 7 µA Wait mode or when output current is low 17
Voltage regulator consumption in Shutdown mode 1 µA Shutdown mode 17
Voltage regulator startup time to reach Normal mode 400 µs 17
Backup mode consumption on VDDBU 2.5 µA Backup mode, current consumption on VDDBU (Table 5-1 footnote 4) 24
Backup mode wake-up time 0.5 ms Backup mode 24
Wait mode wake-up time 10 µs Wait mode 24
ERASE pin hold-high time to reinitialize Flash 220 ms Pin must be tied high more than 220 ms; less than 100 ms is ignored 27
Embedded 32 kHz RC oscillator (slow clock) frequency range 22 42 kHz Low power RC oscillator 264
32.768 kHz crystal oscillator frequency 32.768 kHz Slow clock crystal oscillator 445
3 to 20 MHz crystal oscillator frequency range 3 20 MHz Main clock crystal oscillator 446
Maximum operating speed 96 MHz 1
High-speed pad frequency, HSMCI and SPI clock lines 65 MHz HSMCI and SPI clock lines 25
High-speed pad frequency, other I/O lines 35 MHz Other lines than HSMCI and SPI clock 25
Operating temperature range -40 85 °C Industrial temperature range, LQFP100 package 1137
NRST internal pull-up resistor to VDDIO 100 kΩ Permanent pull-up, printed as about 100 kΩ 26
NRSTB internal pull-up resistor 15 kΩ Permanent pull-up, printed as about 15 kΩ 26
I/O line typical pull-up resistor 100 kΩ Typical value for all I/Os 25
On-die termination series resistance (ODT) 36 Ω Figure 6-1, typical 25
JTAGSEL internal pull-down resistor to GNDBU 15 kΩ Permanent pull-down, printed as about 15 kΩ 26
TST internal pull-down resistor to GND 15 kΩ Permanent pull-down, printed as about 15 kΩ 26
ERASE internal pull-down resistor to GND 15 kΩ Permanent pull-down, printed as about 15 kΩ 26

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the 134

CAD (KiCad official)

  • Symbol: ATSAM3U1CB-AU
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: atsam3u1cb-au-etched.step / atsam3u1cb-au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam3u1cb-au.step / atsam3u1cb-au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1163 pp, sha256 b84d00c06a823c14, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF