ATSAM3N1AB-AU

Microchip Tech · Pre-ordered MCUs · LQFP-48(7x7)

ATSAM3N1AB-AU from Microchip Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ADVREF	power_in	ADC reference voltage input; conversions extend from 0 V to ADVREF, which may equal the analog supply, and an external decoupling capacitor is required for noise filtering.
2	GND	power_in	Ground connection.
3	PB0/AD4	bidirectional	PIO line PB0 multiplexed with ADC analog input AD4 (ADC input range 0 V to ADVREF).
4	PB1/AD5	bidirectional	PIO line PB1 multiplexed with ADC analog input AD5 (ADC input range 0 V to ADVREF).
5	PB2/AD6	bidirectional	PIO line PB2 multiplexed with ADC analog input AD6 and UART1 receive URXD1.
6	PB3/AD7	bidirectional	PIO line PB3 multiplexed with ADC analog input AD7 and UART1 transmit UTXD1.
7	VDDIN	power_in	Supply for the voltage regulator, ADC and DAC; the voltage regulator operates from 1.8 V to 3.6 V.
8	VDDOUT	power_out	Output of the on-chip voltage regulator that powers VDDCORE when the internal regulator is used; its voltage limits are in Section 5.3, which is not in the extracted text.
9	PA17/PGMD5/AD0	bidirectional	PIO line PA17 multiplexed with Fast Flash programming data PGMD5 and ADC analog input AD0.
10	PA18/PGMD6/AD1	bidirectional	PIO line PA18 multiplexed with Fast Flash programming data PGMD6 and ADC analog input AD1.
11	PA19/PGMD7/AD2	bidirectional	PIO line PA19 multiplexed with Fast Flash programming data PGMD7 and ADC analog input AD2 (wake-up WKUP9).
12	PA20/AD3	bidirectional	PIO line PA20 multiplexed with ADC analog input AD3 (wake-up WKUP10).
13	VDDIO	power_in	Supply for peripheral I/O lines, backup part, 32 kHz crystal oscillator and oscillator pads, 1.62 V to 3.6 V; it must always be higher than or equal to VDDCORE.
14	PA16/PGMD4	bidirectional	PIO line PA16 multiplexed with Fast Flash programming data PGMD4.
15	PA15/PGMD3	bidirectional	PIO line PA15 multiplexed with Fast Flash programming data PGMD3.
16	PA14/PGMD2	bidirectional	PIO line PA14 multiplexed with Fast Flash programming data PGMD2 and SPI clock SPCK.
17	PA13/PGMD1	bidirectional	PIO line PA13 multiplexed with Fast Flash programming data PGMD1 and SPI MOSI.
18	VDDCORE	power_in	Core supply powering the processor, embedded memories and peripherals, 1.62 V to 1.95 V.
19	PA12/PGMD0	bidirectional	PIO line PA12 multiplexed with Fast Flash programming data PGMD0 and SPI MISO.
20	PA11/PGMM3	bidirectional	PIO line PA11 multiplexed with programming mode input PGMM3 and SPI NPCS0.
21	PA10/PGMM2	bidirectional	PIO line PA10 multiplexed with programming mode input PGMM2, UART0 transmit UTXD0 and SPI NPCS2.
22	PA9/PGMM1	bidirectional	PIO line PA9 multiplexed with programming mode input PGMM1, UART0 receive URXD0 and SPI NPCS1.
23	PA8/XOUT32/PGMM0	bidirectional	PIO line PA8 multiplexed with programming mode input PGMM0, 32 kHz crystal output XOUT32 and ADC trigger ADTRG.
24	PA7/XIN32/PGMNVALID	bidirectional	PIO line PA7 multiplexed with 32 kHz crystal input XIN32 and the programming data-direction output PGMNVALID (active low).
25	TDI/PB4	bidirectional	JTAG test data input TDI multiplexed with PIO line PB4 (also TWI1 data TWD1).
26	PA6/PGMNOE	bidirectional	PIO line PA6 multiplexed with programming read input PGMNOE (active low).
27	PA5/PGMRDY	bidirectional	PIO line PA5 multiplexed with programming ready output PGMRDY (active high).
28	PA4/PGMNCMD	bidirectional	PIO line PA4 multiplexed with programming command input PGMNCMD (active low) and TWI0 clock TWCK0.
29	NRST	bidirectional	Microcontroller reset, active low, operating as an input or output.
30	TST	input	Test select: low at power-up selects normal operation and high selects test or FFPI mode; it has an internal pull-down of about 15 kΩ and may be left unconnected for normal operation.
31	PA3	bidirectional	PIO line PA3 multiplexed with TWI0 data TWD0 and SPI NPCS3.
32	PA2/PGMEN2	bidirectional	PIO line PA2 multiplexed with programming enable input PGMEN2.
33	VDDIO	power_in	Supply for peripheral I/O lines, 1.62 V to 3.6 V; it must always be higher than or equal to VDDCORE.
34	GND	power_in	Ground connection.
35	PA1/PGMEN1	bidirectional	PIO line PA1 multiplexed with programming enable input PGMEN1 and TC0 output TIOB0.
36	PA0/PGMEN0	bidirectional	PIO line PA0 multiplexed with programming enable input PGMEN0 and TC0 signal TIOA0.
37	TDO/TRACESWO/PB5	output	JTAG test data output TDO, multiplexed with serial-wire trace output TRACESWO and PIO line PB5; outside debug mode it is in input mode, so its internal pull-up must be enabled to avoid floating-input current.
38	JTAGSEL	input	JTAG selection input (active high): with TST low at power-up, a high level enables IEEE 1149.1 boundary scan, and a chip reset is required after it is changed.
39	TMS/SWDIO/PB6	bidirectional	Test mode select TMS for JTAG or serial-wire data SWDIO, multiplexed with PIO line PB6.
40	TCK/SWCLK/PB7	input	Test clock TCK for JTAG or serial-wire clock SWCLK, multiplexed with PIO line PB7.
41	VDDCORE	power_in	Core supply powering the processor, embedded memories and peripherals, 1.62 V to 1.95 V.
42	ERASE/PB12	bidirectional	PIO line PB12 multiplexed with the ERASE pin, whose function is described in Section 6.5 (not in the extracted text).
43	PB10	bidirectional	PIO line PB10 whose Schmitt trigger can be disabled through the PIO registers.
44	PB11	bidirectional	PIO line PB11 whose Schmitt trigger can be disabled through the PIO registers.
45	XOUT/PB8	bidirectional	Main oscillator output XOUT for a 3 to 20 MHz crystal, multiplexed with PIO line PB8.
46	XIN/P/PB9/GMCK	input	Main oscillator input XIN for a 3 to 20 MHz crystal, multiplexed with PIO line PB9 and the programming clock PGMCK.
47	VDDIO	power_in	Supply for peripheral I/O lines, 1.62 V to 3.6 V; it must always be higher than or equal to VDDCORE.
48	VDDPLL	power_in	Supply for the PLL, the Fast RC oscillator and the 3 to 20 MHz oscillators, 1.62 V to 1.95 V.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDDCORE core supply voltage	VDDCORE	1.62		1.95	V		16
VDDIO I/O supply voltage	VDDIO	1.62		3.6	V		16
VDDIN voltage regulator supply voltage	VDDIN	1.8		3.6	V	Voltage Regulator	16
VDDPLL PLL and oscillator supply voltage	VDDPLL	1.62		1.95	V		16
Main supply for ADC and DAC usable		3			V	With Main Supply >= 3 V all peripherals usable; below 3 V ADC and DAC not usable	18
VDDIO minimum operating voltage before VDDCORE reaches VDDCORE(min) at power-up	VDDIO	1.62			V	Power-up sequencing	16
VDDIO rising slope when VDDCORE rises with VDDIO		5			V/ms	VDDCORE rising at the same time as VDDIO	16
VDDIO level at power-up before VDDIN reaches 1.0 V	VDDIO	0.6			V	At power-up, before VDDIN reaches 1.0 V	17
VDDIO relative to VDDIN at startup	VDDIO			0.5	V	VDDIO at or below VDDIN voltage + 0.5 V	17
Voltage regulator static current in Normal mode				700	µA	Normal mode, static current	17
Voltage regulator quiescent current in Wait mode			7		µA	Wait mode	17
Voltage regulator current consumption in Backup mode				1	µA	Backup mode; VDDOUT driven internally to GND	17
Voltage regulator default output voltage	VDDOUT		1.8		V	Default output voltage	17
Voltage regulator start-up time to Normal mode				100	µs	Start-up to Normal mode	17
Backup mode total consumption			3		µA	Backup mode, total current consumption	21
Backup mode wake-up time				0.1	ms	Wake-up from Backup mode	21
Wait mode current consumption			5		µA	5 µA on VDDCORE; 15 µA total with internal voltage regulator; 8 µA total without internal voltage regulator (Wait mode)	21
Wait mode wake-up time				10	µs	Wake-up from Wait mode	21
Supply monitor threshold on VDDIO		1.9		3.4	V	Programmable in 100 mV steps (SMTH)	253
Fast RC low-power oscillator frequency (Slow Clock RC)		22		42	kHz	22-42 kHz Low Power RC Oscillator	249
Slow clock crystal frequency			32.768		kHz	32 kHz crystal oscillator, typical Slow Clock	243
3 to 20 MHz crystal oscillator frequency range		3		20	MHz	3 to 20 MHz oscillator	16
SPI clock pad maximum frequency				45	MHz	High speed pads, SPI clock lines	22
Other I/O line maximum frequency				35	MHz	High speed pads, other lines than SPI clock	22
I/O pull-up and pull-down resistance			100		kΩ	Typical value for all I/Os	22
NRST pull-up resistance to VDDIO			100		kΩ	Permanent pull-up to VDDIO	24
ERASE pin pull-down resistance			100		kΩ	Pull-down to GND	24
JTAGSEL pin pull-down resistance			15		kΩ	Permanent pull-down to GND	23
TST pin pull-down resistance			15		kΩ	Permanent pull-down to GND	23
ERASE pin high time for Flash erase		220			ms	ERASE tied high for Flash erase operation	24
ERASE pin high time ignored				100	ms	ERASE tied high for less than this time is not taken into account	24
External reset length minimum (ERSTL)		60			µs	External reset programmable between 60 µs and 2 s	215
External reset length maximum (ERSTL)				2	s	External reset programmable between 60 µs and 2 s	215
Operating temperature range (Industrial, AU package)		-40		85	°C	Industrial grade, ordering code ATSAM3N1AB-AU	752

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the	129

CAD (KiCad official)

Symbol: ATSAM3N1AB-AU
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: atsam3n1ab-au-etched.step / atsam3n1ab-au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam3n1ab-au.step / atsam3n1ab-au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (766 pp, sha256 6e0c0e7028df8bf3, retrieved 2026-11-13, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ATSAM3N1AB-AU

**Microchip Tech** · Pre-ordered MCUs · LQFP-48(7x7)

ATSAM3N1AB-AU from Microchip Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADVREF | power_in | ADC reference voltage input; conversions extend from 0 V to ADVREF, which may equal the analog supply, and an external decoupling capacitor is required for noise filtering. |
| 2 | GND | power_in | Ground connection. |
| 3 | PB0/AD4 | bidirectional | PIO line PB0 multiplexed with ADC analog input AD4 (ADC input range 0 V to ADVREF). |
| 4 | PB1/AD5 | bidirectional | PIO line PB1 multiplexed with ADC analog input AD5 (ADC input range 0 V to ADVREF). |
| 5 | PB2/AD6 | bidirectional | PIO line PB2 multiplexed with ADC analog input AD6 and UART1 receive URXD1. |
| 6 | PB3/AD7 | bidirectional | PIO line PB3 multiplexed with ADC analog input AD7 and UART1 transmit UTXD1. |
| 7 | VDDIN | power_in | Supply for the voltage regulator, ADC and DAC; the voltage regulator operates from 1.8 V to 3.6 V. |
| 8 | VDDOUT | power_out | Output of the on-chip voltage regulator that powers VDDCORE when the internal regulator is used; its voltage limits are in Section 5.3, which is not in the extracted text. |
| 9 | PA17/PGMD5/AD0 | bidirectional | PIO line PA17 multiplexed with Fast Flash programming data PGMD5 and ADC analog input AD0. |
| 10 | PA18/PGMD6/AD1 | bidirectional | PIO line PA18 multiplexed with Fast Flash programming data PGMD6 and ADC analog input AD1. |
| 11 | PA19/PGMD7/AD2 | bidirectional | PIO line PA19 multiplexed with Fast Flash programming data PGMD7 and ADC analog input AD2 (wake-up WKUP9). |
| 12 | PA20/AD3 | bidirectional | PIO line PA20 multiplexed with ADC analog input AD3 (wake-up WKUP10). |
| 13 | VDDIO | power_in | Supply for peripheral I/O lines, backup part, 32 kHz crystal oscillator and oscillator pads, 1.62 V to 3.6 V; it must always be higher than or equal to VDDCORE. |
| 14 | PA16/PGMD4 | bidirectional | PIO line PA16 multiplexed with Fast Flash programming data PGMD4. |
| 15 | PA15/PGMD3 | bidirectional | PIO line PA15 multiplexed with Fast Flash programming data PGMD3. |
| 16 | PA14/PGMD2 | bidirectional | PIO line PA14 multiplexed with Fast Flash programming data PGMD2 and SPI clock SPCK. |
| 17 | PA13/PGMD1 | bidirectional | PIO line PA13 multiplexed with Fast Flash programming data PGMD1 and SPI MOSI. |
| 18 | VDDCORE | power_in | Core supply powering the processor, embedded memories and peripherals, 1.62 V to 1.95 V. |
| 19 | PA12/PGMD0 | bidirectional | PIO line PA12 multiplexed with Fast Flash programming data PGMD0 and SPI MISO. |
| 20 | PA11/PGMM3 | bidirectional | PIO line PA11 multiplexed with programming mode input PGMM3 and SPI NPCS0. |
| 21 | PA10/PGMM2 | bidirectional | PIO line PA10 multiplexed with programming mode input PGMM2, UART0 transmit UTXD0 and SPI NPCS2. |
| 22 | PA9/PGMM1 | bidirectional | PIO line PA9 multiplexed with programming mode input PGMM1, UART0 receive URXD0 and SPI NPCS1. |
| 23 | PA8/XOUT32/PGMM0 | bidirectional | PIO line PA8 multiplexed with programming mode input PGMM0, 32 kHz crystal output XOUT32 and ADC trigger ADTRG. |
| 24 | PA7/XIN32/PGMNVALID | bidirectional | PIO line PA7 multiplexed with 32 kHz crystal input XIN32 and the programming data-direction output PGMNVALID (active low). |
| 25 | TDI/PB4 | bidirectional | JTAG test data input TDI multiplexed with PIO line PB4 (also TWI1 data TWD1). |
| 26 | PA6/PGMNOE | bidirectional | PIO line PA6 multiplexed with programming read input PGMNOE (active low). |
| 27 | PA5/PGMRDY | bidirectional | PIO line PA5 multiplexed with programming ready output PGMRDY (active high). |
| 28 | PA4/PGMNCMD | bidirectional | PIO line PA4 multiplexed with programming command input PGMNCMD (active low) and TWI0 clock TWCK0. |
| 29 | NRST | bidirectional | Microcontroller reset, active low, operating as an input or output. |
| 30 | TST | input | Test select: low at power-up selects normal operation and high selects test or FFPI mode; it has an internal pull-down of about 15 kΩ and may be left unconnected for normal operation. |
| 31 | PA3 | bidirectional | PIO line PA3 multiplexed with TWI0 data TWD0 and SPI NPCS3. |
| 32 | PA2/PGMEN2 | bidirectional | PIO line PA2 multiplexed with programming enable input PGMEN2. |
| 33 | VDDIO | power_in | Supply for peripheral I/O lines, 1.62 V to 3.6 V; it must always be higher than or equal to VDDCORE. |
| 34 | GND | power_in | Ground connection. |
| 35 | PA1/PGMEN1 | bidirectional | PIO line PA1 multiplexed with programming enable input PGMEN1 and TC0 output TIOB0. |
| 36 | PA0/PGMEN0 | bidirectional | PIO line PA0 multiplexed with programming enable input PGMEN0 and TC0 signal TIOA0. |
| 37 | TDO/TRACESWO/PB5 | output | JTAG test data output TDO, multiplexed with serial-wire trace output TRACESWO and PIO line PB5; outside debug mode it is in input mode, so its internal pull-up must be enabled to avoid floating-input current. |
| 38 | JTAGSEL | input | JTAG selection input (active high): with TST low at power-up, a high level enables IEEE 1149.1 boundary scan, and a chip reset is required after it is changed. |
| 39 | TMS/SWDIO/PB6 | bidirectional | Test mode select TMS for JTAG or serial-wire data SWDIO, multiplexed with PIO line PB6. |
| 40 | TCK/SWCLK/PB7 | input | Test clock TCK for JTAG or serial-wire clock SWCLK, multiplexed with PIO line PB7. |
| 41 | VDDCORE | power_in | Core supply powering the processor, embedded memories and peripherals, 1.62 V to 1.95 V. |
| 42 | ERASE/PB12 | bidirectional | PIO line PB12 multiplexed with the ERASE pin, whose function is described in Section 6.5 (not in the extracted text). |
| 43 | PB10 | bidirectional | PIO line PB10 whose Schmitt trigger can be disabled through the PIO registers. |
| 44 | PB11 | bidirectional | PIO line PB11 whose Schmitt trigger can be disabled through the PIO registers. |
| 45 | XOUT/PB8 | bidirectional | Main oscillator output XOUT for a 3 to 20 MHz crystal, multiplexed with PIO line PB8. |
| 46 | XIN/P/PB9/GMCK | input | Main oscillator input XIN for a 3 to 20 MHz crystal, multiplexed with PIO line PB9 and the programming clock PGMCK. |
| 47 | VDDIO | power_in | Supply for peripheral I/O lines, 1.62 V to 3.6 V; it must always be higher than or equal to VDDCORE. |
| 48 | VDDPLL | power_in | Supply for the PLL, the Fast RC oscillator and the 3 to 20 MHz oscillators, 1.62 V to 1.95 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDDCORE core supply voltage | VDDCORE | 1.62 |  | 1.95 | V |  | 16 |
| VDDIO I/O supply voltage | VDDIO | 1.62 |  | 3.6 | V |  | 16 |
| VDDIN voltage regulator supply voltage | VDDIN | 1.8 |  | 3.6 | V | Voltage Regulator | 16 |
| VDDPLL PLL and oscillator supply voltage | VDDPLL | 1.62 |  | 1.95 | V |  | 16 |
| Main supply for ADC and DAC usable |  | 3 |  |  | V | With Main Supply >= 3 V all peripherals usable; below 3 V ADC and DAC not usable | 18 |
| VDDIO minimum operating voltage before VDDCORE reaches VDDCORE(min) at power-up | VDDIO | 1.62 |  |  | V | Power-up sequencing | 16 |
| VDDIO rising slope when VDDCORE rises with VDDIO |  | 5 |  |  | V/ms | VDDCORE rising at the same time as VDDIO | 16 |
| VDDIO level at power-up before VDDIN reaches 1.0 V | VDDIO | 0.6 |  |  | V | At power-up, before VDDIN reaches 1.0 V | 17 |
| VDDIO relative to VDDIN at startup | VDDIO |  |  | 0.5 | V | VDDIO at or below VDDIN voltage + 0.5 V | 17 |
| Voltage regulator static current in Normal mode |  |  |  | 700 | µA | Normal mode, static current | 17 |
| Voltage regulator quiescent current in Wait mode |  |  | 7 |  | µA | Wait mode | 17 |
| Voltage regulator current consumption in Backup mode |  |  |  | 1 | µA | Backup mode; VDDOUT driven internally to GND | 17 |
| Voltage regulator default output voltage | VDDOUT |  | 1.8 |  | V | Default output voltage | 17 |
| Voltage regulator start-up time to Normal mode |  |  |  | 100 | µs | Start-up to Normal mode | 17 |
| Backup mode total consumption |  |  | 3 |  | µA | Backup mode, total current consumption | 21 |
| Backup mode wake-up time |  |  |  | 0.1 | ms | Wake-up from Backup mode | 21 |
| Wait mode current consumption |  |  | 5 |  | µA | 5 µA on VDDCORE; 15 µA total with internal voltage regulator; 8 µA total without internal voltage regulator (Wait mode) | 21 |
| Wait mode wake-up time |  |  |  | 10 | µs | Wake-up from Wait mode | 21 |
| Supply monitor threshold on VDDIO |  | 1.9 |  | 3.4 | V | Programmable in 100 mV steps (SMTH) | 253 |
| Fast RC low-power oscillator frequency (Slow Clock RC) |  | 22 |  | 42 | kHz | 22-42 kHz Low Power RC Oscillator | 249 |
| Slow clock crystal frequency |  |  | 32.768 |  | kHz | 32 kHz crystal oscillator, typical Slow Clock | 243 |
| 3 to 20 MHz crystal oscillator frequency range |  | 3 |  | 20 | MHz | 3 to 20 MHz oscillator | 16 |
| SPI clock pad maximum frequency |  |  |  | 45 | MHz | High speed pads, SPI clock lines | 22 |
| Other I/O line maximum frequency |  |  |  | 35 | MHz | High speed pads, other lines than SPI clock | 22 |
| I/O pull-up and pull-down resistance |  |  | 100 |  | kΩ | Typical value for all I/Os | 22 |
| NRST pull-up resistance to VDDIO |  |  | 100 |  | kΩ | Permanent pull-up to VDDIO | 24 |
| ERASE pin pull-down resistance |  |  | 100 |  | kΩ | Pull-down to GND | 24 |
| JTAGSEL pin pull-down resistance |  |  | 15 |  | kΩ | Permanent pull-down to GND | 23 |
| TST pin pull-down resistance |  |  | 15 |  | kΩ | Permanent pull-down to GND | 23 |
| ERASE pin high time for Flash erase |  | 220 |  |  | ms | ERASE tied high for Flash erase operation | 24 |
| ERASE pin high time ignored |  |  |  | 100 | ms | ERASE tied high for less than this time is not taken into account | 24 |
| External reset length minimum (ERSTL) |  | 60 |  |  | µs | External reset programmable between 60 µs and 2 s | 215 |
| External reset length maximum (ERSTL) |  |  |  | 2 | s | External reset programmable between 60 µs and 2 s | 215 |
| Operating temperature range (Industrial, AU package) |  | -40 |  | 85 | °C | Industrial grade, ordering code ATSAM3N1AB-AU | 752 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the | 129 |

## CAD (KiCad official)

- Symbol: `ATSAM3N1AB-AU`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `atsam3n1ab-au-etched.step` / `atsam3n1ab-au-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atsam3n1ab-au.step` / `atsam3n1ab-au.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/atsam3n1ab-au-datasheet.pdf) (766 pp, sha256 `6e0c0e7028df8bf3`, retrieved 2026-11-13, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/atsam3n1ab-au-datasheet.pdf)