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ATSAM3A8CA-AU

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Microchip Tech Pre-ordered MCUs, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatsam3a8ca-aufactory-2.0.0extractor-text

Verified ATSAM3A8CA-AU

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAM3A8CA-AU · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 1459-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-g_7d3lk5/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atsam3a8ca-au.kicad_sym✓ atsam3a8ca-au.kicad_mod✓ atsam3a8ca-au.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers atsam3a8ca-au: viewers · Ray 4d ago
atsam3a8ca-au-etched.glb Publish 0.1.0 · Ray 4d ago
atsam3a8ca-au-etched.step atsam3a8ca-au: factory component page (tier=mfr) · Ray 4d ago
atsam3a8ca-au-hero.glb atsam3a8ca-au: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
atsam3a8ca-au-hero.overlay.json Publish 0.1.0 · Ray 4d ago
atsam3a8ca-au.glb Publish 0.1.0 · Ray 4d ago
atsam3a8ca-au.kicad_mod Publish 0.1.0 · Ray 4d ago
atsam3a8ca-au.kicad_sym Publish 0.1.0 · Ray 4d ago
atsam3a8ca-au.lbr Publish 0.1.0 · Ray 4d ago
atsam3a8ca-au.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 100 pins · Ray 4d ago

ATSAM3A8CA-AU

Microchip Tech · Pre-ordered MCUs · LQFP-100(14x14)

ATSAM3A8CA-AU from Microchip Tech, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB26 bidirectional PIO port B line 26, with TC0 TCLK0 as peripheral B function.
2 PA9 bidirectional PIO port A line 9, with UART UTXD as peripheral A function.
3 PA10 bidirectional PIO port A line 10, general-purpose I/O.
4 PA11 bidirectional PIO port A line 11, with ADC ADTRG as peripheral B function.
5 PA12 bidirectional PIO port A line 12, general-purpose I/O.
6 PA13 bidirectional PIO port A line 13, general-purpose I/O.
7 PA14 bidirectional PIO port A line 14, with SSC TK as peripheral B function.
8 PA15 bidirectional PIO port A line 15, with SSC TF as peripheral B function.
9 PA17 bidirectional PIO port A line 17, with TWI0 TWD0 as peripheral A function.
10 VDDCORE power_in Core supply powering the core, embedded memories and peripherals, 1.62V to 1.95V.
11 VDDIO power_in Peripheral I/O lines supply, 1.62V to 3.6V, must be higher than or equal to VDDCORE.
12 GND power_in Ground common to VDDCORE and VDDIO supplies.
13 PA0 bidirectional PIO port A line 0, general-purpose I/O.
14 PA1 bidirectional PIO port A line 1, general-purpose I/O.
15 PA5 bidirectional PIO port A line 5, with TC0 TIOA2 as peripheral A function.
16 PA7 bidirectional PIO port A line 7, with TC0 TCLK2 as peripheral A function.
17 PA8 bidirectional PIO port A line 8, with UART URXD as peripheral A function.
18 PB28 bidirectional PIO port B line 28, general-purpose I/O.
19 PB29 bidirectional PIO port B line 29, general-purpose I/O.
20 PB30 bidirectional PIO port B line 30, general-purpose I/O.
21 PB31 bidirectional PIO port B line 31, general-purpose I/O.
22 GNDPLL power_in Separate ground pin for the VDDPLL supply.
23 VDDPLL power_in Powers PLL A, UPLL and the 3-20 MHz oscillator, 1.62V to 1.95V.
24 XOUT output 3-20 MHz crystal oscillator output.
25 XIN input 3-20 MHz crystal oscillator input.
26 DHSDP bidirectional USB high-speed differential data line D+ of the UTMI+ port.
27 DHSDM bidirectional USB high-speed differential data line D- of the UTMI+ port.
28 VBUS power_in USB VBus bus power measurement input.
29 VBG passive Bias/band-gap pin of the USB transceiver, listed in the pinout without further description.
30 VDDUTMI power_in Powers the UTMI+ interface, 3.0V to 3.6V, 3.3V nominal.
31 DFSDP bidirectional USB full-speed differential data line D+.
32 DFSDM bidirectional USB full-speed differential data line D-.
33 GNDUTMI power_in Separate ground pin for the VDDUTMI supply.
34 VDDCORE power_in Core supply powering the core, embedded memories and peripherals, 1.62V to 1.95V.
35 JTAGSEL input JTAG selection input, active high; SW-DP or JTAG-DP mode is selected when low, and a chip reset is needed after changing it.
36 XIN32 input 32.768 kHz crystal oscillator input, or external clock input in bypass mode; leave unconnected if the crystal is not used.
37 XOUT32 output 32.768 kHz crystal oscillator output; leave unconnected if the crystal is not used.
38 TST input Test select input with permanent ~15 kOhm pull-down; low at power-up gives normal operation, high gives test or FFPI mode.
39 VDDBU power_in Powers the slow clock oscillator and part of the system controller, 1.62V to 3.6V, supplied before or with VDDIO and VDDCORE.
40 FWUP input Wake-up input (renamed from WAKEUP); must be high with JTAGSEL during boundary scan.
41 GND power_in Ground common to VDDCORE and VDDIO supplies.
42 VDDOUT power_out Output of the internal 1.8V voltage regulator.
43 VDDIN power_in Powers the voltage regulator input, shared with the ADC and DAC.
44 GND power_in Ground common to VDDCORE and VDDIO supplies.
45 VDDCORE power_in Core supply powering the core, embedded memories and peripherals, 1.62V to 1.95V.
46 PB27 bidirectional PIO port B line 27, with TC0 TIOB0 as peripheral B function.
47 NRST bidirectional Microcontroller reset, active low input/output.
48 PA18 bidirectional PIO port A line 18, with TWI0 TWCK0 as peripheral A function.
49 PA19 bidirectional PIO port A line 19, with HSMCI MCCK as peripheral A function.
50 PA20 bidirectional PIO port A line 20, with HSMCI MCCDA as peripheral A function.
51 VDDANA power_in Powers the ADC and DAC cells, 2.0V to 3.6V.
52 GNDANA power_in Separate ground pin for the VDDANA supply.
53 ADVREF input ADC reference voltage input.
54 PB15 bidirectional PIO port B line 15, general-purpose I/O.
55 PB16 bidirectional PIO port B line 16, with TC1 TCLK5 as peripheral A function.
56 PA16 bidirectional PIO port A line 16, with ADC input AD7 and SSC TD as peripheral B function.
57 PA24 bidirectional PIO port A line 24, with ADC input AD6 and HSMCI MCDA3 as peripheral A function.
58 PA23 bidirectional PIO port A line 23, with ADC input AD5 and HSMCI MCDA2 as peripheral A function.
59 PA22 bidirectional PIO port A line 22, with ADC input AD4 and HSMCI MCDA1 as peripheral A function.
60 PA6 bidirectional PIO port A line 6, with ADC input AD3 and TC0 TIOB2 as peripheral A function.
61 PA4 bidirectional PIO port A line 4, with ADC input AD2 and TC0 TCLK1 as peripheral A function.
62 PA3 bidirectional PIO port A line 3, with ADC input AD1/WKUP1 and TC0 TIOB1 as peripheral A function.
63 PA2 bidirectional PIO port A line 2, with ADC input AD0 and TC0 TIOA1 as peripheral A function.
64 PB12 bidirectional PIO port B line 12, with ADC input AD8 and TWI1 TWD1 as peripheral A function.
65 PB13 bidirectional PIO port B line 13, with ADC input AD9 and TWI1 TWCK1 as peripheral A function.
66 PB17 bidirectional PIO port B line 17, with ADC input AD10 and SSC RF as peripheral A function.
67 PB18 bidirectional PIO port B line 18, with ADC input AD11 and SSC RD as peripheral A function.
68 PB19 bidirectional PIO port B line 19, with ADC input AD12 and SSC RK as peripheral A function.
69 PB20 bidirectional PIO port B line 20, with ADC input AD13 and SPI0 NPCS1 as peripheral B function.
70 PB21 bidirectional PIO port B line 21, with ADC input AD14/WKUP13 and SPI0 NPCS2 as peripheral B function.
71 VDDCORE power_in Core supply powering the core, embedded memories and peripherals, 1.62V to 1.95V.
72 VDDIO power_in Peripheral I/O lines supply, 1.62V to 3.6V, must be higher than or equal to VDDCORE.
73 GND power_in Ground common to VDDCORE and VDDIO supplies.
74 PA21 bidirectional PIO port A line 21, with HSMCI MCDA0 as peripheral A function.
75 PA25 bidirectional PIO port A line 25, with SPI0 MISO as peripheral A function.
76 PA26 bidirectional PIO port A line 26, with SPI0 MOSI as peripheral A function.
77 PA27 bidirectional PIO port A line 27, with SPI0 SPCK as peripheral A function.
78 PA28 bidirectional PIO port A line 28, with SPI0 NPCS0 as peripheral A function.
79 PA29 bidirectional PIO port A line 29, with SPI0 NPCS1 as peripheral A function.
80 PB0 bidirectional PIO port B line 0, with TC1 TIOA3 as peripheral B function.
81 PB1 bidirectional PIO port B line 1, with TC1 TIOB3 as peripheral B function.
82 PB2 bidirectional PIO port B line 2, with TC1 TIOA4 as peripheral B function.
83 PB3 bidirectional PIO port B line 3, with TC1 TIOB4 as peripheral B function.
84 PB4 bidirectional PIO port B line 4, with TC1 TIOA5 as peripheral B function.
85 PB5 bidirectional PIO port B line 5, with TC1 TIOB5 as peripheral B function.
86 PB6 bidirectional PIO port B line 6, general-purpose I/O.
87 PB7 bidirectional PIO port B line 7, general-purpose I/O.
88 PB8 bidirectional PIO port B line 8, general-purpose I/O.
89 VDDCORE power_in Core supply powering the core, embedded memories and peripherals, 1.62V to 1.95V.
90 VDDIO power_in Peripheral I/O lines supply, 1.62V to 3.6V, must be higher than or equal to VDDCORE.
91 GND power_in Ground common to VDDCORE and VDDIO supplies.
92 PB9 bidirectional PIO port B line 9, general-purpose I/O.
93 PB10 bidirectional PIO port B line 10, with UOTGHS UOTGVBOF as peripheral A function.
94 PB11 bidirectional PIO port B line 11, with UOTGHS UOTGID as peripheral A function.
95 PC0 bidirectional PIO port C line 0, default ERASE pin that can erase Flash when set high.
96 PB14 bidirectional PIO port B line 14, general-purpose I/O.
97 PB22 bidirectional PIO port B line 22, general-purpose I/O.
98 PB23 bidirectional PIO port B line 23, with SPI0 NPCS3 as peripheral B function.
99 PB24 bidirectional PIO port B line 24, general-purpose I/O.
100 PB25 bidirectional PIO port B line 25, with TC0 TIOA0 as peripheral B function.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the 140

CAD (KiCad official)

  • Symbol: ATSAM3A8CA-AU
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: atsam3a8ca-au-etched.step / atsam3a8ca-au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam3a8ca-au.step / atsam3a8ca-au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1459 pp, sha256 aafc34e215ce68af, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF