component
ATMEGA8A-MU
Public Made by Adomby adom
Microchip Tech ATMEL & AVR, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ATMEGA8A-MU
Microchip Tech · ATMEL & AVR · QFN-32-EP(5x5)
ATMEGA8A-MU from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD3/INT1 | bidirectional | Port D bit 3, a bi-directional I/O with internal pull-up that can also serve as External Interrupt 1 input. |
| 2 | PD4/XCK/T0 | bidirectional | Port D bit 4, a bi-directional I/O with internal pull-up that can also serve as USART external clock XCK or Timer/Counter0 external counter input T0. |
| 3 | GND | power_in | Ground reference for the digital supply. |
| 4 | VCC | power_in | Digital supply voltage, specified at 2.7 - 5.5V. |
| 5 | GND | power_in | Ground reference for the digital supply. |
| 6 | VCC | power_in | Digital supply voltage, specified at 2.7 - 5.5V. |
| 7 | PB6 (XTAL1/TOSC1) | input | Port B bit 6, used as input to the inverting oscillator amplifier (XTAL1) or as Timer Oscillator pin 1 depending on clock fuse settings. |
| 8 | PB7 (XTAL2/TOSC2) | output | Port B bit 7, used as output from the inverting oscillator amplifier (XTAL2) or as Timer Oscillator pin 2 depending on clock fuse settings. |
| 9 | PD5/T1 | bidirectional | Port D bit 5, a bi-directional I/O with internal pull-up that can also serve as Timer/Counter1 external counter input T1. |
| 10 | PD6/AIN0 | bidirectional | Port D bit 6, a bi-directional I/O that serves as Analog Comparator positive input AIN0, with the internal pull-up switched off when used as comparator input. |
| 11 | PD7/AIN1 | bidirectional | Port D bit 7, a bi-directional I/O that serves as Analog Comparator negative input AIN1, with the internal pull-up switched off when used as comparator input. |
| 12 | PB0/ICP1 | bidirectional | Port B bit 0, a bi-directional I/O with internal pull-up that can act as Input Capture Pin ICP1 for Timer/Counter1. |
| 13 | PB1 (OC1A) | bidirectional | Port B bit 1, a bi-directional I/O with internal pull-up that can serve as Timer/Counter1 Output Compare A output OC1A. |
| 14 | PB2 (SS/OC1B) | bidirectional | Port B bit 2, a bi-directional I/O with internal pull-up that serves as SPI slave select SS or Timer/Counter1 Output Compare B output OC1B. |
| 15 | PB3 (MOSI/OC2) | bidirectional | Port B bit 3, a bi-directional I/O with internal pull-up that serves as SPI MOSI or Timer/Counter2 Output Compare output OC2. |
| 16 | PB4 (MISO) | bidirectional | Port B bit 4, a bi-directional I/O with internal pull-up that serves as SPI master input or slave output MISO. |
| 17 | PB5 (SCK) | bidirectional | Port B bit 5, a bi-directional I/O with internal pull-up that serves as SPI clock SCK. |
| 18 | AVCC | power_in | Supply voltage pin for the A/D converter and ADC channels 6 and 7, to be connected to VCC even when the ADC is not used. |
| 19 | ADC6 | passive | ADC analog input channel 6, available only in the TQFP and VQFN packages and powered from the analog supply. |
| 20 | AREF | passive | Analog reference pin for the A/D converter. |
| 21 | GND | power_in | Ground reference for the digital supply. |
| 22 | ADC7 | passive | ADC analog input channel 7, available only in the TQFP and VQFN packages and powered from the analog supply. |
| 23 | PC0 (ADC0) | bidirectional | Port C bit 0, a bi-directional I/O with internal pull-up that can also serve as ADC input channel 0 using analog power. |
| 24 | PC1 (ADC1) | bidirectional | Port C bit 1, a bi-directional I/O with internal pull-up that can also serve as ADC input channel 1 using analog power. |
| 25 | PC2 (ADC2) | bidirectional | Port C bit 2, a bi-directional I/O with internal pull-up that can also serve as ADC input channel 2 using analog power. |
| 26 | PC3 (ADC3) | bidirectional | Port C bit 3, a bi-directional I/O with internal pull-up that can also serve as ADC input channel 3 using analog power. |
| 27 | PC4 (SDA/ADC4) | bidirectional | Port C bit 4, a bi-directional I/O with internal pull-up that serves as Two-wire Serial Data SDA or ADC input channel 4 using digital power. |
| 28 | PC5 (SCL/ADC5) | bidirectional | Port C bit 5, a bi-directional I/O with internal pull-up that serves as Two-wire Serial Clock SCL or ADC input channel 5 using digital power. |
| 29 | PC6 (RESET) | input | Reset input when the RSTDISBL fuse is unprogrammed; a low level longer than the minimum pulse length generates a reset, otherwise it is a normal I/O pin with different electrical characteristics. |
| 30 | PD0 (RXD) | bidirectional | Port D bit 0, a bi-directional I/O with internal pull-up that serves as USART receive data input RXD when the receiver is enabled. |
| 31 | PD1 (TXD) | bidirectional | Port D bit 1, a bi-directional I/O with internal pull-up that serves as USART transmit data output TXD when the transmitter is enabled. |
| 32 | PD2 (INT0) | bidirectional | Port D bit 2, a bi-directional I/O with internal pull-up that can serve as External Interrupt 0 input INT0. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | -55 | 125 | °C | 232 | |||
| Storage Temperature | -65 | 150 | °C | 232 | |||
| Voltage on RESET with respect to Ground | -0.5 | 13 | V | 232 | |||
| Maximum Operating Voltage | 6 | V | 232 | ||||
| DC Current per I/O Pin | 40 | mA | 232 | ||||
| DC Current VCC and GND Pins | 300 | mA | 232 | ||||
| Digital supply voltage | VCC | 2.7 | 5.5 | V | TA = -40°C to 85°C | 232 | |
| Operating temperature range | -40 | 85 | °C | Industrial range | 232 | ||
| Output Low Voltage (Ports B,C,D) | VOL | 0.9 | V | IOL = 20mA, VCC = 5V | 232 | ||
| Output Low Voltage (Ports B,C,D) | VOL | 0.6 | V | IOL = 10mA, VCC = 3V | 232 | ||
| Output High Voltage (Ports B,C,D) | VOH | 4.2 | V | IOH = -20mA, VCC = 5V | 232 | ||
| Output High Voltage (Ports B,C,D) | VOH | 2.2 | V | IOH = -10mA, VCC = 3V | 232 | ||
| Input Leakage Current I/O Pin (low) | IIL | 1 | µA | Vcc = 5.5V, pin low (absolute value) | 232 | ||
| Input Leakage Current I/O Pin (high) | IIH | 1 | µA | Vcc = 5.5V, pin high (absolute value) | 232 | ||
| Reset Pull-up Resistor | RRST | 30 | 80 | k | 233 | ||
| I/O Pin Pull-up Resistor | Rpu | 20 | 50 | k | 233 | ||
| Power Supply Current Active | ICC | 5 | mA | Active 4MHz, VCC = 3V | 233 | ||
| Power Supply Current Active | ICC | 15 | mA | Active 8MHz, VCC = 5V | 233 | ||
| Power Supply Current Idle | ICC | 2 | mA | Idle 4MHz, VCC = 3V | 233 | ||
| Power Supply Current Idle | ICC | 7 | mA | Idle 8MHz, VCC = 5V | 233 | ||
| Power Supply Current Power-down | ICC | 28 | µA | Power-down mode, WDT enabled, VCC = 3V | 233 | ||
| Power Supply Current Power-down | ICC | 3 | µA | Power-down mode, WDT disabled, VCC = 3V | 233 | ||
| Analog Comparator Input Offset Voltage | VACIO | 40 | mV | VCC = 5V, Vin = VCC/2 | 233 | ||
| Analog Comparator Input Leakage Current | IACLK | -50 | 50 | nA | VCC = 5V, Vin = VCC/2 | 233 | |
| Analog Comparator Propagation Delay | tACPD | 750 | ns | VCC = 2.7V | 233 | ||
| Analog Comparator Propagation Delay | tACPD | 500 | ns | VCC = 5.0V | 233 | ||
| Oscillator Frequency | 1/tCLCL | 0 | 8 | MHz | VCC = 2.7V to 5.5V | 234 | |
| Oscillator Frequency | 1/tCLCL | 0 | 16 | MHz | VCC = 4.5V to 5.5V | 234 | |
| Clock Period | tCLCL | 125 | ns | VCC = 2.7V to 5.5V | 234 | ||
| Clock Period | tCLCL | 62.5 | ns | VCC = 4.5V to 5.5V | 234 | ||
| Minimum pulse width on RESET Pin | tRST | 1.5 | µs | 235 | |||
| Power-on Reset Threshold Voltage (rising) | VPOT | 1.4 | 2.3 | V | rising | 235 | |
| Power-on Reset Threshold Voltage (falling) | VPOT | 1.3 | 2.3 | V | falling | 235 | |
| Brown-out Reset Threshold Voltage | VBOT | 2.4 | 2.6 | 2.9 | V | BODLEVEL = 1 | 235 |
| Brown-out Reset Threshold Voltage | VBOT | 3.7 | 4 | 4.5 | V | BODLEVEL = 0 | 235 |
| Bandgap reference voltage | VBG | 1.15 | 1.23 | 1.35 | V | 235 | |
| Output Low-voltage (TWI) | VOL | 0 | 0.4 | V | 3mA sink current | 236 | |
| Spikes Suppressed by Input Filter | tSP | 0 | 50 | ns | 236 | ||
| Input Current each I/O Pin (TWI) | Ii | -10 | 10 | µA | 0.1VCC < Vi < 0.9VCC | 236 | |
| Capacitance for each I/O Pin (TWI) | Ci | 10 | pF | 236 | |||
| SCL Clock Frequency | fSCL | 0 | 400 | kHz | fCK > max(16fSCL, 250kHz) | 236 | |
| Hold Time (repeated) START Condition | tHD;STA | 4 | µs | fSCL <= 100kHz | 236 | ||
| Hold Time (repeated) START Condition | tHD;STA | 0.6 | µs | fSCL > 100kHz | 236 | ||
| Low Period of the SCL Clock | tLOW | 4.7 | µs | fSCL <= 100kHz | 236 | ||
| Low Period of the SCL Clock | tLOW | 1.3 | µs | fSCL > 100kHz | 236 | ||
| High period of the SCL clock | tHIGH | 4 | µs | fSCL <= 100kHz | 236 | ||
| High period of the SCL clock | tHIGH | 0.6 | µs | fSCL > 100kHz | 236 | ||
| Data setup time | tSU;DAT | 250 | ns | fSCL <= 100kHz | 236 | ||
| Data setup time | tSU;DAT | 100 | ns | fSCL > 100kHz | 236 | ||
| Rise Time Master (SPI) | 3.6 | ns | Master | 237 | |||
| Setup Master (SPI) | 10 | ns | Master | 237 | |||
| Hold Master (SPI) | 10 | ns | Master | 237 | |||
| SCK to out Master (SPI) | 10 | ns | Master | 237 | |||
| SCK to out high Master (SPI) | 10 | ns | Master | 237 | |||
| SS low to out Slave (SPI) | 15 | ns | Slave | 237 | |||
| Absolute accuracy (ADC) | 1.75 | LSB | Single Ended Conversion, VREF = 4V, VCC = 4V, ADC clock = 200kHz | 239 | |||
| Integral Non-linearity (INL) | 0.75 | LSB | Single Ended Conversion, VREF = 4V, VCC = 4V, ADC clock = 200kHz | 239 | |||
| Clock Frequency (ADC) | 50 | 1000 | kHz | 239 | |||
| Internal Voltage Reference (ADC) | VINT | 2.3 | 2.56 | 2.8 | V | 239 |
CAD (KiCad official)
- Symbol:
ATMEGA8A-MU - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
atmega8a-mu-etched.step/atmega8a-mu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega8a-mu.step/atmega8a-mu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (327 pp, sha256
e10f0e392857e034, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).