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ATMEGA809-MUR

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatmega809-murfactory-2.0.0extractor-text

Verified ATMEGA809-MUR

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA809-MUR · VQFN-48-EP(6x6) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 543-page datasheet
  • ✓distributor: lcsc C1512794, digikey 150-ATMEGA809-MURTR-ND, mouser 556-ATMEGA809-MUR
  • ✓family: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-eyzq76qv/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.533)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega809-mur.kicad_sym✓ atmega809-mur.kicad_mod✓ atmega809-mur.step
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ATMEGA809-MUR

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-48-EP(6x6)

ATMEGA809-MUR from Microchip Tech, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA5 bidirectional General-purpose I/O pin PA5 on PORTA (VDD power domain), also usable for USART0 RxD (alternate position), SPI0 MISO and CCL/TCA0 WO5 alternate functions per the multiplexing table.
2 PA6 bidirectional General-purpose I/O pin PA6 on PORTA (VDD power domain), also usable for USART0 XCK (alternate position), SPI0 SCK and an alternate event/output function per the multiplexing table.
3 PA7 bidirectional General-purpose I/O pin PA7 on PORTA (VDD power domain), also usable for CLKOUT, AC0 OUT, USART0 XDIR (alternate position), SPI0 SS and EVOUTA (alternate position).
4 PB0 bidirectional General-purpose I/O pin PB0 on PORTB, also usable for USART3 TxD and TCA0 WO0 (alternate position) per the multiplexing table.
5 PB1 bidirectional General-purpose I/O pin PB1 on PORTB, also usable for USART3 RxD and TCA0 WO1 (alternate position) per the multiplexing table.
6 PB2 bidirectional General-purpose I/O pin PB2 on PORTB, also usable for USART3 XCK, TCA0 WO2 (alternate position) and EVOUTB per the multiplexing table.
7 PB3 bidirectional General-purpose I/O pin PB3 on PORTB, also usable for USART3 XDIR and TCA0 WO3 (alternate position) per the multiplexing table.
8 PB4 bidirectional General-purpose I/O pin PB4 on PORTB, also usable for USART3 TxD (alternate position), TCA0 WO4 (alternate position) and TCB2 WO (alternate position) per the multiplexing table.
9 PB5 bidirectional General-purpose I/O pin PB5 on PORTB, also usable for USART3 RxD (alternate position), TCA0 WO5 (alternate position) and TCB3 WO per the multiplexing table.
10 PC0 bidirectional General-purpose I/O pin PC0 on PORTC (VDD power domain), also usable for USART1 TxD, SPI0 MOSI (alternate position), TCA0 WO0 (alternate position) and TCB2 WO per the multiplexing table.
11 PC1 bidirectional General-purpose I/O pin PC1 on PORTC (VDD power domain), also usable for USART1 RxD, SPI0 MISO (alternate position), TCA0 WO1 (alternate position) and TCB3 WO (alternate position).
12 PC2 bidirectional General-purpose I/O pin PC2 on PORTC (VDD power domain), also usable for TWI0 SDA (master), USART1 XCK, SPI0 SCK (alternate position), TCA0 WO2 (alternate position) and EVOUTC.
13 PC3 bidirectional General-purpose I/O pin PC3 on PORTC (VDD power domain), also usable for TWI0 SCL (master), USART1 XDIR, SPI0 SS (alternate position) and TCA0 WO3 (alternate position).
14 VDD power_in Supply voltage for the digital core and VDD-domain I/O; the device operates from 1.8 V to 5.5 V per the ordering information.
15 GND power_in Ground reference for the device.
16 PC4 bidirectional General-purpose I/O pin PC4 on PORTC, also usable for USART1 TxD (alternate position) and TCA0 WO4 (alternate position).
17 PC5 bidirectional General-purpose I/O pin PC5 on PORTC, also usable for USART1 RxD (alternate position) and TCA0 WO5 (alternate position).
18 PC6 bidirectional General-purpose I/O pin PC6 on PORTC, also usable for USART1 XCK (alternate position) and TCB1 OUT (alternate position).
19 PC7 bidirectional General-purpose I/O pin PC7 on PORTC, also usable for USART1 XDIR (alternate position) and EVOUTC (alternate position).
20 PD0 bidirectional General-purpose I/O pin PD0 on PORTD, also usable as analog input AIN0, TCA0 WO0 (alternate position) and AC0 input 2 (CCL LUT2-IN0).
21 PD1 bidirectional General-purpose I/O pin PD1 on PORTD, also usable as analog input AIN1, AC0 positive input P3, TCA0 WO1 (alternate position) and CCL LUT2-IN1.
22 PD2 bidirectional General-purpose I/O pin PD2 on PORTD, also usable as analog input AIN2, AC0 positive input P0, TCA0 WO2 (alternate position), EVOUTD and CCL LUT2-IN2.
23 PD3 bidirectional General-purpose I/O pin PD3 on PORTD, also usable as analog input AIN3, AC0 negative input N0, TCA0 WO3 (alternate position) and CCL LUT2-OUT.
24 PD4 bidirectional General-purpose I/O pin PD4 on PORTD, also usable as analog input AIN4, AC0 positive input P1 and TCA0 WO4 (alternate position).
25 PD5 bidirectional General-purpose I/O pin PD5 on PORTD, also usable as analog input AIN5, AC0 negative input N1 and TCA0 WO5 (alternate position).
26 PD6 bidirectional General-purpose I/O pin PD6 on PORTD, also usable as analog input AIN6, AC0 positive input P2 and CCL LUT2-OUT (alternate position).
27 PD7 bidirectional General-purpose I/O pin PD7 on PORTD, also usable as the external voltage reference input VREFA, analog input AIN7, AC0 negative input N2 and EVOUTD (alternate position).
28 AVDD power_in Supply for the analog domain (ADC, analog peripherals) and the GPIO on the AVDD power domain; the device operates from 1.8 V to 5.5 V per the ordering information.
29 GND power_in Ground reference for the device.
30 PE0 bidirectional General-purpose I/O pin PE0 on PORTE, also usable as analog input AIN8, SPI0 MOSI (alternate position) and TCA0 WO0 (alternate position).
31 PE1 bidirectional General-purpose I/O pin PE1 on PORTE, also usable as analog input AIN9, SPI0 MISO (alternate position) and TCA0 WO1 (alternate position).
32 PE2 bidirectional General-purpose I/O pin PE2 on PORTE, also usable as analog input AIN10, SPI0 SCK (alternate position), TCA0 WO2 (alternate position) and EVOUTE.
33 PE3 bidirectional General-purpose I/O pin PE3 on PORTE, also usable as analog input AIN11, SPI0 SS (alternate position) and TCA0 WO3 (alternate position).
34 PF0 (TOSC1) passive General-purpose I/O pin PF0 on PORTF, shared with the 32.768 kHz crystal oscillator input TOSC1; also usable for USART2 TxD (alternate position) and TCA0 WO0 (alternate position).
35 PF1 (TOSC2) passive General-purpose I/O pin PF1 on PORTF, shared with the 32.768 kHz crystal oscillator output TOSC2; also usable for USART2 RxD (alternate position) and TCA0 WO1 (alternate position).
36 PF2 bidirectional General-purpose I/O pin PF2 on PORTF, also usable for TWI0 SDA (slave), analog input AIN12, USART2 XCK (alternate position), TCA0 WO2 (alternate position) and EVOUTF.
37 PF3 bidirectional General-purpose I/O pin PF3 on PORTF, also usable for TWI0 SCL (slave), analog input AIN13, USART2 XDIR (alternate position) and TCA0 WO3 (alternate position).
38 PF4 bidirectional General-purpose I/O pin PF4 on PORTF, also usable as analog input AIN14, USART2 TxD (alternate position) and TCA0 WO4 (alternate position).
39 PF5 bidirectional General-purpose I/O pin PF5 on PORTF, also usable as analog input AIN15, USART2 RxD (alternate position) and TCA0 WO5 (alternate position).
40 PF6 (RESET) bidirectional General-purpose I/O pin PF6 on PORTF that is the external Reset pin when the RSTPINCFG fuse selects RESET, also usable for USART2 XCK (alternate position) and CCL LUT3-OUT (alternate position).
41 UPDI bidirectional Unified Program and Debug Interface pin used for programming and debugging the device.
42 VDD power_in Supply voltage for the digital core and VDD-domain I/O; the device operates from 1.8 V to 5.5 V per the ordering information.
43 GND power_in Ground reference for the device.
44 PA0 (EXTCLK) bidirectional General-purpose I/O pin PA0 on PORTA (AVDD power domain), also usable as external clock input EXTCLK, USART0 TxD (alternate position), TCA0 WO0 and CCL LUT0-IN0 and as an event input.
45 PA1 bidirectional General-purpose I/O pin PA1 on PORTA (AVDD power domain), also usable for USART0 RxD, TCA0 WO1 and CCL LUT0-IN1.
46 PA2 bidirectional General-purpose I/O pin PA2 on PORTA (AVDD power domain), also usable for TWI0 SDA (master), USART0 XCK, TCA0 WO2, TCB0 WO and EVOUTA and CCL LUT0-IN2.
47 PA3 bidirectional General-purpose I/O pin PA3 on PORTA (AVDD power domain), also usable for TWI0 SCL (master), USART0 XDIR, TCA0 WO3, TCB1 WO and CCL LUT0-OUT.
48 PA4 bidirectional General-purpose I/O pin PA4 on PORTA (AVDD power domain), also usable for USART0 TxD (alternate position), SPI0 MOSI and TCA0 WO4.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-48-EP(6x6)
Category Embedded Processors & Controllers
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage 1.8 5.5 V ATmega809-MUR, Ordering Information table (Supply Voltage column) 513
Temperature Range -40 85 °C ATmega809-MUR (-40°C to +85°C, Tape & Reel), Ordering Information table 513
Max. CPU Speed 20 MHz ATmega809-MUR, Ordering Information table (Max. CPU Speed column), supply 1.8-5.5V 513

CAD (KiCad official)

  • Symbol: ATMEGA809-MUR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: atmega809-mur-etched.step / atmega809-mur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega809-mur.step / atmega809-mur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (543 pp, sha256 fe2ccf6f4621a1cd, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF