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ATMEGA809-MU

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Microchip Tech Pre-ordered MCUs, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatmega809-mufactory-2.0.0extractor-text

Verified ATMEGA809-MU

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA809-MU · VQFN-48-EP(6x6) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 543-page datasheet
  • ✓distributor: lcsc C1019279, digikey 150-ATMEGA809-MU-ND, mouser 556-ATMEGA809-MU
  • ✓family: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-cyxu3civ/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.533)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega809-mu.kicad_sym✓ atmega809-mu.kicad_mod✓ atmega809-mu.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers atmega809-mu: viewers · Ray 5d ago
atmega809-mu-etched.glb Publish 0.1.0 · Ray 5d ago
atmega809-mu-etched.step atmega809-mu: factory component page (tier=mfr) · Ray 5d ago
atmega809-mu-hero.glb atmega809-mu: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
atmega809-mu-hero.overlay.json Publish 0.1.0 · Ray 5d ago
atmega809-mu.glb Publish 0.1.0 · Ray 5d ago
atmega809-mu.kicad_mod Publish 0.1.0 · Ray 5d ago
atmega809-mu.kicad_sym Publish 0.1.0 · Ray 5d ago
atmega809-mu.lbr Publish 0.1.0 · Ray 5d ago
atmega809-mu.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 49 pins · Ray 5d ago

ATMEGA809-MU

Microchip Tech · Pre-ordered MCUs · VQFN-48-EP(6x6)

ATMEGA809-MU from Microchip Tech, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA5 bidirectional General-purpose I/O pin PA5 with alternate functions USART0 RxD (alternate position), SPI0 MISO and TCA0 WO5 per the multiplexing table.
2 PA6 bidirectional General-purpose I/O pin PA6 with alternate functions USART0 XCK (alternate position) and SPI0 SCK.
3 PA7 bidirectional General-purpose I/O pin PA7 with alternate functions CLKOUT, AC0 OUT, USART0 XDIR (alternate position), SPI0 SS and EVOUTA (alternate position).
4 PB0 bidirectional General-purpose I/O pin PB0 with alternate functions USART3 TxD and TCA0 WO0 (alternate position).
5 PB1 bidirectional General-purpose I/O pin PB1 with alternate functions USART3 RxD and TCA0 WO1 (alternate position).
6 PB2 bidirectional General-purpose I/O pin PB2 with alternate functions USART3 XCK, TCA0 WO2 (alternate position) and EVOUTB.
7 PB3 bidirectional General-purpose I/O pin PB3 with alternate functions USART3 XDIR and TCA0 WO3 (alternate position).
8 PB4 bidirectional General-purpose I/O pin PB4 with alternate functions USART3 TxD (alternate position), TCA0 WO4 (alternate position) and TCB2 WO (alternate position).
9 PB5 bidirectional General-purpose I/O pin PB5 with alternate functions USART3 RxD (alternate position), TCA0 WO5 (alternate position) and TCB3 WO.
10 PC0 bidirectional General-purpose I/O pin PC0 with alternate functions USART1 TxD, SPI0 MOSI (alternate position), TCA0 WO0 (alternate position), TCB2 WO and CCL LUT1 IN0.
11 PC1 bidirectional General-purpose I/O pin PC1 with alternate functions USART1 RxD, SPI0 MISO (alternate position), TCA0 WO1 (alternate position), TCB3 WO (alternate position) and CCL LUT1 IN1.
12 PC2 bidirectional General-purpose I/O pin PC2 with alternate functions USART1 XCK, SPI0 SCK (alternate position), TWI0 SDA (alternate position), TCA0 WO2 (alternate position), EVOUTC and CCL LUT1 IN2.
13 PC3 bidirectional General-purpose I/O pin PC3 with alternate functions USART1 XDIR, SPI0 SS (alternate position), TWI0 SCL (alternate position), TCA0 WO3 (alternate position) and CCL LUT1 OUT.
14 VDD power_in Positive supply pin for the device; the device operates from 1.8 V to 5.5 V per the ordering information.
15 GND power_in Ground reference pin for the device.
16 PC4 bidirectional General-purpose I/O pin PC4 with alternate functions USART1 TxD (alternate position) and TCA0 WO4 (alternate position).
17 PC5 bidirectional General-purpose I/O pin PC5 with alternate functions USART1 RxD (alternate position) and TCA0 WO5 (alternate position).
18 PC6 bidirectional General-purpose I/O pin PC6 with alternate functions USART1 XCK (alternate position) and CCL LUT1 OUT (alternate position).
19 PC7 bidirectional General-purpose I/O pin PC7 with alternate functions USART1 XDIR (alternate position) and EVOUTC (alternate position).
20 PD0 bidirectional General-purpose I/O pin PD0 with alternate functions AIN0, TCA0 WO0 (alternate position) and CCL LUT2 IN0.
21 PD1 bidirectional General-purpose I/O pin PD1 with alternate functions AIN1, AC0 P3, TCA0 WO1 (alternate position) and CCL LUT2 IN1.
22 PD2 bidirectional General-purpose I/O pin PD2 with alternate functions AIN2, AC0 P0, TCA0 WO2 (alternate position), EVOUTD and CCL LUT2 IN2.
23 PD3 bidirectional General-purpose I/O pin PD3 with alternate functions AIN3, AC0 N0, TCA0 WO3 (alternate position) and CCL LUT2 OUT.
24 PD4 bidirectional General-purpose I/O pin PD4 with alternate functions AIN4, AC0 P1 and TCA0 WO4 (alternate position).
25 PD5 bidirectional General-purpose I/O pin PD5 with alternate functions AIN5, AC0 N1 and TCA0 WO5 (alternate position).
26 PD6 bidirectional General-purpose I/O pin PD6 with alternate functions AIN6, AC0 P2 and CCL LUT2 OUT (alternate position).
27 PD7 bidirectional General-purpose I/O pin PD7 with alternate functions VREFA, AIN7, AC0 N2 and EVOUTD (alternate position).
28 AVDD power_in Supply pin for the analog domain, powering the GPIO pins on the AVDD power domain within the 1.8 V to 5.5 V device range.
29 GND power_in Ground reference pin for the device.
30 PE0 bidirectional General-purpose I/O pin PE0 with alternate functions AIN8, SPI0 MOSI (alternate position) and TCA0 WO0 (alternate position).
31 PE1 bidirectional General-purpose I/O pin PE1 with alternate functions AIN9, SPI0 MISO (alternate position) and TCA0 WO1 (alternate position).
32 PE2 bidirectional General-purpose I/O pin PE2 with alternate functions AIN10, SPI0 SCK (alternate position), TCA0 WO2 (alternate position) and EVOUTE.
33 PE3 bidirectional General-purpose I/O pin PE3 with alternate functions AIN11, SPI0 SS (alternate position) and TCA0 WO3 (alternate position).
34 PF0 bidirectional General-purpose I/O pin PF0 that serves as the TOSC1 crystal oscillator input, with alternate functions USART2 TxD, TCA0 WO0 (alternate position) and CCL LUT3 IN0.
35 PF1 bidirectional General-purpose I/O pin PF1 that serves as the TOSC2 crystal oscillator output, with alternate functions USART2 RxD, TCA0 WO1 (alternate position) and CCL LUT3 IN1.
36 PF2 bidirectional General-purpose I/O pin PF2 with alternate functions TWI (slave SDA, alternate position), AIN12, USART2 XCK, TCA0 WO2 (alternate position), EVOUTF and CCL LUT3 IN2.
37 PF3 bidirectional General-purpose I/O pin PF3 with alternate functions TWI (slave SCL, alternate position), AIN13, USART2 XDIR, TCA0 WO3 (alternate position) and CCL LUT3 OUT.
38 PF4 bidirectional General-purpose I/O pin PF4 with alternate functions AIN14, USART2 TxD (alternate position), TCA0 WO4 (alternate position) and TCB0 WO (alternate position).
39 PF5 bidirectional General-purpose I/O pin PF5 with alternate functions AIN15, USART2 RxD (alternate position), TCA0 WO5 (alternate position) and TCB1 WO (alternate position).
40 PF6 bidirectional General-purpose I/O pin PF6 that becomes the external RESET pin when SYSCFG0.RSTPINCFG is set to RESET, with alternate functions USART2 XCK (alternate position) and CCL LUT3 OUT (alternate position).
41 UPDI bidirectional Unified Program and Debug Interface pin used for programming and debugging the device.
42 VDD power_in Positive supply pin for the device; the device operates from 1.8 V to 5.5 V per the ordering information.
43 GND power_in Ground reference pin for the device.
44 PA0 bidirectional General-purpose I/O pin PA0 with alternate functions EXTCLK, USART0 TxD, TCA0 WO0 and CCL LUT0 IN0.
45 PA1 bidirectional General-purpose I/O pin PA1 with alternate functions USART0 RxD, TCA0 WO1 and CCL LUT0 IN1.
46 PA2 bidirectional General-purpose I/O pin PA2 with alternate functions TWI0 SDA (master), USART0 XCK, TCA0 WO2, TCB0 WO, EVOUTA and CCL LUT0 IN2.
47 PA3 bidirectional General-purpose I/O pin PA3 with alternate functions TWI0 SCL (master), USART0 XDIR, TCA0 WO3, TCB1 WO and CCL LUT0 OUT.
48 PA4 bidirectional General-purpose I/O pin PA4 with alternate functions USART0 TxD (alternate position), SPI0 MOSI and TCA0 WO4.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-48-EP(6x6)
Category Embedded Processors & Controllers
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (ATmega809-MU ordering row) 1.8 5.5 V 513
Temperature range (ATmega809-MU ordering row) -40 85 °C 513
Max CPU speed (ATmega809-MU ordering row) 20 MHz 513

CAD (KiCad official)

  • Symbol: ATMEGA809-MU
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: atmega809-mu-etched.step / atmega809-mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega809-mu.step / atmega809-mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (543 pp, sha256 fe2ccf6f4621a1cd, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF