component
ATMEGA809-AU
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ATMEGA809-AU
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-48(7x7)
ATMEGA809-AU from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA5 | bidirectional | GPIO PA5 with alternates USART0 RxD (alternate position), SPI0 MISO and TCA0 WO5, and it can be used as an event input and external interrupt source. |
| 2 | PA6 | bidirectional | GPIO PA6 with alternates USART0 XCK (alternate position), SPI0 SCK and CCL LUT0 OUT, and it can be used as an event input and external interrupt source. |
| 3 | PA7 | bidirectional | GPIO PA7 with alternates CLKOUT, AC0 OUT, USART0 XDIR (alternate position), SPI0 SS and EVSYS output EVOUTA (alternate position). |
| 4 | PB0 | bidirectional | GPIO PB0 with alternates USART3 TxD and TCA0 WO0 (alternate position). |
| 5 | PB1 | bidirectional | GPIO PB1 with alternates USART3 RxD and TCA0 WO1 (alternate position). |
| 6 | PB2 | bidirectional | GPIO PB2 with alternates USART3 XCK, TCA0 WO2 (alternate position) and EVSYS output EVOUTB. |
| 7 | PB3 | bidirectional | GPIO PB3 with alternates USART3 XDIR and TCA0 WO3 (alternate position). |
| 8 | PB4 | bidirectional | GPIO PB4 with alternates USART3 TxD, TCA0 WO4 and TCB2 WO (alternate positions). |
| 9 | PB5 | bidirectional | GPIO PB5 with alternates USART3 RxD, TCA0 WO5 and TCB3 WO (alternate positions). |
| 10 | PC0 | bidirectional | GPIO PC0 with alternates USART1 TxD, SPI0 MOSI, TCA0 WO0, TCB2 WO and CCL LUT1-IN0. |
| 11 | PC1 | bidirectional | GPIO PC1 with alternates USART1 RxD, SPI0 MISO, TCA0 WO1, TCB3 WO and CCL LUT1-IN1. |
| 12 | PC2 | bidirectional | GPIO PC2 with alternates USART1 XCK, SPI0 SCK, TWI SDA (host, alternate position), TCA0 WO2, EVSYS output EVOUTC and CCL LUT1-IN2. |
| 13 | PC3 | bidirectional | GPIO PC3 with alternates USART1 XDIR, SPI0 SS, TWI SCL (host, alternate position), TCA0 WO3 and CCL LUT1 OUT. |
| 14 | VDD | power_in | Supply pin for the VDD power domain; device supply range is 1.8-5.5 V per the ordering information. |
| 15 | GND | power_in | Ground reference pin. |
| 16 | PC4 | bidirectional | GPIO PC4 with alternates USART1 TxD (alternate position) and TCA0 WO4 (alternate position). |
| 17 | PC5 | bidirectional | GPIO PC5 with alternates USART1 RxD (alternate position) and TCA0 WO5 (alternate position). |
| 18 | PC6 | bidirectional | GPIO PC6 with alternates USART1 XCK (alternate position) and CCL LUT1 OUT (alternate position). |
| 19 | PC7 | bidirectional | GPIO PC7 with alternates USART1 XDIR (alternate position) and EVSYS output EVOUTC (alternate position). |
| 20 | PD0 | bidirectional | GPIO PD0 with alternates ADC0 AIN0, TCA0 WO0 (alternate position) and CCL LUT2-IN0. |
| 21 | PD1 | bidirectional | GPIO PD1 with alternates ADC0 AIN1, AC0 P3, TCA0 WO1 (alternate position) and CCL LUT2-IN1. |
| 22 | PD2 | bidirectional | GPIO PD2 with alternates ADC0 AIN2, AC0 P0, TCA0 WO2 (alternate position), EVSYS output EVOUTD and CCL LUT2-IN2. |
| 23 | PD3 | bidirectional | GPIO PD3 with alternates ADC0 AIN3, AC0 N0, TCA0 WO3 (alternate position) and CCL LUT2 OUT. |
| 24 | PD4 | bidirectional | GPIO PD4 with alternates ADC0 AIN4, AC0 P1 and TCA0 WO4 (alternate position). |
| 25 | PD5 | bidirectional | GPIO PD5 with alternates ADC0 AIN5, AC0 N1 and TCA0 WO5 (alternate position). |
| 26 | PD6 | bidirectional | GPIO PD6 with alternates ADC0 AIN6, AC0 P2 and CCL LUT2 OUT (alternate position). |
| 27 | PD7 | bidirectional | GPIO PD7 with alternates ADC0 VREFA, ADC0 AIN7, AC0 N2 and EVSYS output EVOUTD (alternate position). |
| 28 | AVDD | power_in | Analog supply pin for the AVDD power domain, which supplies the analog functions such as the ADC and AC. |
| 29 | GND | power_in | Ground reference pin. |
| 30 | PE0 | bidirectional | GPIO PE0 with alternates ADC0 AIN8, SPI0 MOSI (alternate position) and TCA0 WO0 (alternate position). |
| 31 | PE1 | bidirectional | GPIO PE1 with alternates ADC0 AIN9, SPI0 MISO (alternate position) and TCA0 WO1 (alternate position). |
| 32 | PE2 | bidirectional | GPIO PE2 with alternates ADC0 AIN10, SPI0 SCK (alternate position), TCA0 WO2 (alternate position) and EVSYS output EVOUTE. |
| 33 | PE3 | bidirectional | GPIO PE3 with alternates ADC0 AIN11, SPI0 SS (alternate position) and TCA0 WO3 (alternate position). |
| 34 | PF0 (TOSC1) | bidirectional | GPIO PF0 with alternates TOSC1 (crystal/clock input for the 32.768 kHz oscillator), USART2 TxD (alternate position), TCA0 WO0 (alternate position) and CCL LUT3-IN0. |
| 35 | PF1 (TOSC2) | bidirectional | GPIO PF1 with alternates TOSC2 (crystal connection for the 32.768 kHz oscillator), USART2 RxD (alternate position), TCA0 WO1 (alternate position) and CCL LUT3-IN1. |
| 36 | PF2 | bidirectional | GPIO PF2 with alternates TWI SDA (client, alternate position), ADC0 AIN12, USART2 XCK (alternate position), TCA0 WO2 (alternate position), EVSYS output EVOUTF and CCL LUT3-IN2. |
| 37 | PF3 | bidirectional | GPIO PF3 with alternates TWI SCL (client, alternate position), ADC0 AIN13, USART2 XDIR (alternate position), TCA0 WO3 (alternate position) and CCL LUT3 OUT. |
| 38 | PF4 | bidirectional | GPIO PF4 with alternates ADC0 AIN14, USART2 TxD (alternate position), TCA0 WO4 (alternate position) and TCB0 WO (alternate position). |
| 39 | PF5 | bidirectional | GPIO PF5 with alternates ADC0 AIN15, USART2 RxD (alternate position), TCA0 WO5 (alternate position) and TCB1 WO (alternate position). |
| 40 | PF6 (RESET) | bidirectional | GPIO PF6, which is the external RESET pin when the RSTPINCFG fuse selects RESET, and otherwise has alternates USART2 XCK (alternate position) and CCL LUT3 OUT (alternate position). |
| 41 | UPDI | bidirectional | Unified Program and Debug Interface pin used for programming and debugging the device. |
| 42 | VDD | power_in | Supply pin for the VDD power domain; device supply range is 1.8-5.5 V per the ordering information. |
| 43 | GND | power_in | Ground reference pin. |
| 44 | PA0 (EXTCLK) | bidirectional | GPIO PA0 with alternates EXTCLK (external clock input), USART0 TxD (alternate position), TCA0 WO0 and CCL LUT0-IN0. |
| 45 | PA1 | bidirectional | GPIO PA1 with alternates USART0 RxD, TCA0 WO1 and CCL LUT0-IN1. |
| 46 | PA2 | bidirectional | GPIO PA2 with alternates TWI SDA (host, default), USART0 XCK, TCA0 WO2, TCB0 WO, EVSYS output EVOUTA and CCL LUT0-IN2. |
| 47 | PA3 | bidirectional | GPIO PA3 with alternates TWI SCL (host, default), USART0 XDIR, TCA0 WO3, TCB1 WO and CCL LUT0 OUT. |
| 48 | PA4 | bidirectional | GPIO PA4 with alternates USART0 TxD (alternate position), SPI0 MOSI and TCA0 WO4. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (ATmega809-AU, 48-pin TQFP, -40°C to +85°C grade) | 1.8 | 5.5 | V | 520 | |||
| Temperature Range (ATmega809-AU) | -40 | 85 | °C | 520 | |||
| Max. CPU Speed (ATmega809-AU) | 20 | MHz | 520 |
CAD (KiCad official)
- Symbol:
ATMEGA809-AU - Footprint:
Package_QFP:TQFP-48_7x7mm_P0.5mm - 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
atmega809-au-etched.step/atmega809-au-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega809-au.step/atmega809-au.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (552 pp, sha256
e4bbeee766cda6b4, retrieved 2026-10-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATMEGA809-AU
**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · TQFP-48(7x7)
ATMEGA809-AU from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA5 | bidirectional | GPIO PA5 with alternates USART0 RxD (alternate position), SPI0 MISO and TCA0 WO5, and it can be used as an event input and external interrupt source. |
| 2 | PA6 | bidirectional | GPIO PA6 with alternates USART0 XCK (alternate position), SPI0 SCK and CCL LUT0 OUT, and it can be used as an event input and external interrupt source. |
| 3 | PA7 | bidirectional | GPIO PA7 with alternates CLKOUT, AC0 OUT, USART0 XDIR (alternate position), SPI0 SS and EVSYS output EVOUTA (alternate position). |
| 4 | PB0 | bidirectional | GPIO PB0 with alternates USART3 TxD and TCA0 WO0 (alternate position). |
| 5 | PB1 | bidirectional | GPIO PB1 with alternates USART3 RxD and TCA0 WO1 (alternate position). |
| 6 | PB2 | bidirectional | GPIO PB2 with alternates USART3 XCK, TCA0 WO2 (alternate position) and EVSYS output EVOUTB. |
| 7 | PB3 | bidirectional | GPIO PB3 with alternates USART3 XDIR and TCA0 WO3 (alternate position). |
| 8 | PB4 | bidirectional | GPIO PB4 with alternates USART3 TxD, TCA0 WO4 and TCB2 WO (alternate positions). |
| 9 | PB5 | bidirectional | GPIO PB5 with alternates USART3 RxD, TCA0 WO5 and TCB3 WO (alternate positions). |
| 10 | PC0 | bidirectional | GPIO PC0 with alternates USART1 TxD, SPI0 MOSI, TCA0 WO0, TCB2 WO and CCL LUT1-IN0. |
| 11 | PC1 | bidirectional | GPIO PC1 with alternates USART1 RxD, SPI0 MISO, TCA0 WO1, TCB3 WO and CCL LUT1-IN1. |
| 12 | PC2 | bidirectional | GPIO PC2 with alternates USART1 XCK, SPI0 SCK, TWI SDA (host, alternate position), TCA0 WO2, EVSYS output EVOUTC and CCL LUT1-IN2. |
| 13 | PC3 | bidirectional | GPIO PC3 with alternates USART1 XDIR, SPI0 SS, TWI SCL (host, alternate position), TCA0 WO3 and CCL LUT1 OUT. |
| 14 | VDD | power_in | Supply pin for the VDD power domain; device supply range is 1.8-5.5 V per the ordering information. |
| 15 | GND | power_in | Ground reference pin. |
| 16 | PC4 | bidirectional | GPIO PC4 with alternates USART1 TxD (alternate position) and TCA0 WO4 (alternate position). |
| 17 | PC5 | bidirectional | GPIO PC5 with alternates USART1 RxD (alternate position) and TCA0 WO5 (alternate position). |
| 18 | PC6 | bidirectional | GPIO PC6 with alternates USART1 XCK (alternate position) and CCL LUT1 OUT (alternate position). |
| 19 | PC7 | bidirectional | GPIO PC7 with alternates USART1 XDIR (alternate position) and EVSYS output EVOUTC (alternate position). |
| 20 | PD0 | bidirectional | GPIO PD0 with alternates ADC0 AIN0, TCA0 WO0 (alternate position) and CCL LUT2-IN0. |
| 21 | PD1 | bidirectional | GPIO PD1 with alternates ADC0 AIN1, AC0 P3, TCA0 WO1 (alternate position) and CCL LUT2-IN1. |
| 22 | PD2 | bidirectional | GPIO PD2 with alternates ADC0 AIN2, AC0 P0, TCA0 WO2 (alternate position), EVSYS output EVOUTD and CCL LUT2-IN2. |
| 23 | PD3 | bidirectional | GPIO PD3 with alternates ADC0 AIN3, AC0 N0, TCA0 WO3 (alternate position) and CCL LUT2 OUT. |
| 24 | PD4 | bidirectional | GPIO PD4 with alternates ADC0 AIN4, AC0 P1 and TCA0 WO4 (alternate position). |
| 25 | PD5 | bidirectional | GPIO PD5 with alternates ADC0 AIN5, AC0 N1 and TCA0 WO5 (alternate position). |
| 26 | PD6 | bidirectional | GPIO PD6 with alternates ADC0 AIN6, AC0 P2 and CCL LUT2 OUT (alternate position). |
| 27 | PD7 | bidirectional | GPIO PD7 with alternates ADC0 VREFA, ADC0 AIN7, AC0 N2 and EVSYS output EVOUTD (alternate position). |
| 28 | AVDD | power_in | Analog supply pin for the AVDD power domain, which supplies the analog functions such as the ADC and AC. |
| 29 | GND | power_in | Ground reference pin. |
| 30 | PE0 | bidirectional | GPIO PE0 with alternates ADC0 AIN8, SPI0 MOSI (alternate position) and TCA0 WO0 (alternate position). |
| 31 | PE1 | bidirectional | GPIO PE1 with alternates ADC0 AIN9, SPI0 MISO (alternate position) and TCA0 WO1 (alternate position). |
| 32 | PE2 | bidirectional | GPIO PE2 with alternates ADC0 AIN10, SPI0 SCK (alternate position), TCA0 WO2 (alternate position) and EVSYS output EVOUTE. |
| 33 | PE3 | bidirectional | GPIO PE3 with alternates ADC0 AIN11, SPI0 SS (alternate position) and TCA0 WO3 (alternate position). |
| 34 | PF0 (TOSC1) | bidirectional | GPIO PF0 with alternates TOSC1 (crystal/clock input for the 32.768 kHz oscillator), USART2 TxD (alternate position), TCA0 WO0 (alternate position) and CCL LUT3-IN0. |
| 35 | PF1 (TOSC2) | bidirectional | GPIO PF1 with alternates TOSC2 (crystal connection for the 32.768 kHz oscillator), USART2 RxD (alternate position), TCA0 WO1 (alternate position) and CCL LUT3-IN1. |
| 36 | PF2 | bidirectional | GPIO PF2 with alternates TWI SDA (client, alternate position), ADC0 AIN12, USART2 XCK (alternate position), TCA0 WO2 (alternate position), EVSYS output EVOUTF and CCL LUT3-IN2. |
| 37 | PF3 | bidirectional | GPIO PF3 with alternates TWI SCL (client, alternate position), ADC0 AIN13, USART2 XDIR (alternate position), TCA0 WO3 (alternate position) and CCL LUT3 OUT. |
| 38 | PF4 | bidirectional | GPIO PF4 with alternates ADC0 AIN14, USART2 TxD (alternate position), TCA0 WO4 (alternate position) and TCB0 WO (alternate position). |
| 39 | PF5 | bidirectional | GPIO PF5 with alternates ADC0 AIN15, USART2 RxD (alternate position), TCA0 WO5 (alternate position) and TCB1 WO (alternate position). |
| 40 | PF6 (RESET) | bidirectional | GPIO PF6, which is the external RESET pin when the RSTPINCFG fuse selects RESET, and otherwise has alternates USART2 XCK (alternate position) and CCL LUT3 OUT (alternate position). |
| 41 | UPDI | bidirectional | Unified Program and Debug Interface pin used for programming and debugging the device. |
| 42 | VDD | power_in | Supply pin for the VDD power domain; device supply range is 1.8-5.5 V per the ordering information. |
| 43 | GND | power_in | Ground reference pin. |
| 44 | PA0 (EXTCLK) | bidirectional | GPIO PA0 with alternates EXTCLK (external clock input), USART0 TxD (alternate position), TCA0 WO0 and CCL LUT0-IN0. |
| 45 | PA1 | bidirectional | GPIO PA1 with alternates USART0 RxD, TCA0 WO1 and CCL LUT0-IN1. |
| 46 | PA2 | bidirectional | GPIO PA2 with alternates TWI SDA (host, default), USART0 XCK, TCA0 WO2, TCB0 WO, EVSYS output EVOUTA and CCL LUT0-IN2. |
| 47 | PA3 | bidirectional | GPIO PA3 with alternates TWI SCL (host, default), USART0 XDIR, TCA0 WO3, TCB1 WO and CCL LUT0 OUT. |
| 48 | PA4 | bidirectional | GPIO PA4 with alternates USART0 TxD (alternate position), SPI0 MOSI and TCA0 WO4. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (ATmega809-AU, 48-pin TQFP, -40°C to +85°C grade) | | 1.8 | | 5.5 | V | | 520 |
| Temperature Range (ATmega809-AU) | | -40 | | 85 | °C | | 520 |
| Max. CPU Speed (ATmega809-AU) | | | | 20 | MHz | | 520 |
## CAD (KiCad official)
- Symbol: `ATMEGA809-AU`
- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`
- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `atmega809-au-etched.step` / `atmega809-au-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atmega809-au.step` / `atmega809-au.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/ATmega808-09-1608-09-DataSheet-DS40002172C.pdf) (552 pp, sha256 `e4bbeee766cda6b4`, retrieved 2026-10-24, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/atmega809-au-datasheet.pdf)