component
ATMEGA808-MU
Public Made by Adomby adom
Microchip Tech Pre-ordered MCUs, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownATMEGA808-MU
Microchip Tech · Pre-ordered MCUs · VQFN-32-EP(5x5)
ATMEGA808-MU from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA3 | bidirectional | PORTA pin 3 GPIO with TWI SCL (host/client), USART0 XDIR, TCA0 WO3, TCB1 WO and CCL 0-OUT functions. |
| 2 | PA4 | bidirectional | PORTA pin 4 GPIO with SPI0 MOSI, TCA0 WO4 and alternate USART0 TxD functions. |
| 3 | PA5 | bidirectional | PORTA pin 5 GPIO with SPI0 MISO, TCA0 WO5 and alternate USART0 RxD functions. |
| 4 | PA6 | bidirectional | PORTA pin 6 GPIO with SPI0 SCK and alternate USART0 XCK and CCL 0-OUT functions. |
| 5 | PA7 | bidirectional | PORTA pin 7 GPIO with CLKOUT, AC0 OUT, SPI0 SS and alternate USART0 XDIR and EVOUTA functions. |
| 6 | PC0 | bidirectional | PORTC pin 0 GPIO with USART1 TxD, TCB2 WO and CCL 1-IN0 functions. |
| 7 | PC1 | bidirectional | PORTC pin 1 GPIO with USART1 RxD, TCB3 WO (alternate) and CCL 1-IN1 functions. |
| 8 | PC2 | bidirectional | PORTC pin 2 GPIO with TWI SDA (host/client), USART1 XCK, EVOUTC and CCL 1-IN2 functions. |
| 9 | PC3 | bidirectional | PORTC pin 3 GPIO with TWI SCL (host/client), USART1 XDIR and CCL 1-OUT functions. |
| 10 | PD0 | bidirectional | PORTD pin 0 GPIO with ADC0 input AIN0 and CCL 2-IN0 function. |
| 11 | PD1 | bidirectional | PORTD pin 1 GPIO with ADC0 input AIN1, AC0 input P3 and CCL 2-IN1 function. |
| 12 | PD2 | bidirectional | PORTD pin 2 GPIO with ADC0 input AIN2, AC0 input P0, EVOUTD and CCL 2-IN2 function. |
| 13 | PD3 | bidirectional | PORTD pin 3 GPIO with ADC0 input AIN3, AC0 input N0 and CCL 2-OUT function. |
| 14 | PD4 | bidirectional | PORTD pin 4 GPIO with ADC0 input AIN4 and AC0 input P1. |
| 15 | PD5 | bidirectional | PORTD pin 5 GPIO with ADC0 input AIN5 and AC0 input N1. |
| 16 | PD6 | bidirectional | PORTD pin 6 GPIO with ADC0 input AIN6 and AC0 input P2 (fully asynchronous pin-change detection). |
| 17 | PD7 | bidirectional | PORTD pin 7 GPIO with external reference input VREFA, ADC0 input AIN7 and AC0 input N2. |
| 18 | AVDD | power_in | Analog supply input powering the AVDD-domain GPIO pins and analog functions. |
| 19 | GND | power_in | Ground. |
| 20 | PF0 | bidirectional | PORTF pin 0 GPIO with 32.768 kHz crystal oscillator input TOSC1, USART2 TxD and CCL 3-IN0 functions. |
| 21 | PF1 | bidirectional | PORTF pin 1 GPIO with 32.768 kHz crystal oscillator output TOSC2, USART2 RxD and CCL 3-IN1 functions. |
| 22 | PF2 | bidirectional | PORTF pin 2 GPIO with TWI SDA (client), ADC0 input AIN12, USART2 XCK, EVOUTF and CCL 3-IN2 functions. |
| 23 | PF3 | bidirectional | PORTF pin 3 GPIO with TWI SCL (client), ADC0 input AIN13, USART2 XDIR and CCL 3-OUT functions. |
| 24 | PF4 | bidirectional | PORTF pin 4 GPIO with ADC0 input AIN14 and alternate USART2 TxD, TCA0 WO4 and TCB0 WO functions. |
| 25 | PF5 | bidirectional | PORTF pin 5 GPIO with ADC0 input AIN15 and alternate USART2 RxD, TCA0 WO5 and TCB1 WO functions. |
| 26 | PF6 (RESET) | bidirectional | PORTF pin 6 that serves as the active-low RESET input when the RSTPINCFG fuse selects RESET, otherwise a GPIO. |
| 27 | UPDI | bidirectional | Unified Program and Debug Interface pin used for programming and debugging. |
| 28 | VDD | power_in | Digital supply input, 1.8V to 5.5V operating range per the ordering table. |
| 29 | GND | power_in | Ground. |
| 30 | PA0 (EXTCLK) | bidirectional | PORTA pin 0 GPIO with external clock input EXTCLK, USART0 TxD, TCA0 WO0 and CCL 0-IN0 functions. |
| 31 | PA1 | bidirectional | PORTA pin 1 GPIO with USART0 RxD, TCA0 WO1 and CCL 0-IN1 functions. |
| 32 | PA2 | bidirectional | PORTA pin 2 GPIO with TWI SDA (host/client), USART0 XCK, TCA0 WO2, TCB0 WO, EVOUTA and CCL 0-IN2 functions. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 1.8 | 5.5 | V | Ordering table, ATmega808-MU | 520 | |
| Operating Temperature Range | -40 | 85 | °C | Ordering table, ATmega808-MU | 520 | ||
| Maximum CPU Speed | 20 | MHz | Ordering table, ATmega808-MU | 520 |
CAD (KiCad official)
- Symbol:
ATMEGA808-MU - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
atmega808-mu-etched.step/atmega808-mu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega808-mu.step/atmega808-mu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (552 pp, sha256
e4bbeee766cda6b4, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).