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ATMEGA808-AUR

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleratmega808-aurfactory-2.0.0extractor-text

Verified ATMEGA808-AUR

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 32 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA808-AUR · TQFP-32(7x7) · 32 pins
  • ✓copper: 32 copper pads, none touching another net
  • ✓datasheet: all 32 pin names found in the 552-page datasheet
  • ✓distributor: lcsc C2055533, digikey 150-ATMEGA808-AURTR-ND, mouser 556-ATMEGA808-AUR
  • ✓family: TQFP-32_7x7mm_P0.8mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-z8gmjnfa/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.529)
  • ✓pads: 32 pins = 32 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 32 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 45 kB, viewers/symbol.html 23 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega808-aur.kicad_sym✓ atmega808-aur.kicad_mod✓ atmega808-aur.step
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ATMEGA808-AUR

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-32(7x7)

ATMEGA808-AUR from Microchip Tech, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose I/O pin PA3 with alternate functions USART0 XDIR, TWI0 SCL (host), TCA0 WO3, TCB1 WO and CCL LUT1 OUT, and it can be used as an event input and external interrupt source.
2 PA4 bidirectional General-purpose I/O pin PA4 with alternate functions USART0 TxD (alternate position), SPI0 MOSI, and TCA0 WO4, and it can be used as an event input and external interrupt source.
3 PA5 bidirectional General-purpose I/O pin PA5 with alternate functions USART0 RxD (alternate position), SPI0 MISO, and TCA0 WO5, and it can be used as an event input and external interrupt source.
4 PA6 bidirectional General-purpose I/O pin PA6 with alternate functions USART0 XCK (alternate position), SPI0 SCK, and CCL LUT0 OUT (alternate position), and it can be used as an event input and external interrupt source.
5 PA7 bidirectional General-purpose I/O pin PA7 with alternate functions CLKOUT, AC0 OUT, USART0 XDIR (alternate position), SPI0 SS, and EVSYS EVOUTA (alternate position), and it can be used as an event input and external interrupt source.
6 PC0 bidirectional General-purpose I/O pin PC0 with alternate functions USART1 TxD, SPI0 MOSI (alternate position), TCA0 WO0 (alternate position), TCB2 WO (default position), and CCL LUT1 IN0.
7 PC1 bidirectional General-purpose I/O pin PC1 with alternate functions USART1 RxD, SPI0 MISO (alternate position), TCA0 WO1 (alternate position), TCB3 WO (alternate position), and CCL LUT1 IN1.
8 PC2 bidirectional General-purpose I/O pin PC2 with alternate functions TWI0 SDA (host, alternate position), USART1 XCK, SPI0 SCK (alternate position), TCA0 WO2 (alternate position), EVSYS EVOUTC, and CCL LUT1 IN2.
9 PC3 bidirectional General-purpose I/O pin PC3 with alternate functions TWI0 SCL (host, alternate position), USART1 XDIR, SPI0 SS (alternate position), TCA0 WO3 (alternate position), and CCL LUT1 OUT.
10 PD0 bidirectional General-purpose I/O pin PD0 with alternate functions ADC0 AIN0, TCA0 WO0 (alternate position), and CCL LUT2 IN0; it can be used as an event input and external interrupt source.
11 PD1 bidirectional General-purpose I/O pin PD1 with alternate functions ADC0 AIN1, AC0 P3, TCA0 WO1 (alternate position), and CCL LUT2 IN1.
12 PD2 bidirectional General-purpose I/O pin PD2 with alternate functions ADC0 AIN2, AC0 P0, TCA0 WO2 (alternate position), EVSYS EVOUTD, and CCL LUT2 IN2.
13 PD3 bidirectional General-purpose I/O pin PD3 with alternate functions ADC0 AIN3, AC0 N0, TCA0 WO3 (alternate position), and CCL LUT2 OUT.
14 PD4 bidirectional General-purpose I/O pin PD4 with alternate functions ADC0 AIN4, AC0 P1, and TCA0 WO4 (alternate position).
15 PD5 bidirectional General-purpose I/O pin PD5 with alternate functions ADC0 AIN5, AC0 N1, and TCA0 WO5 (alternate position).
16 PD6 bidirectional General-purpose I/O pin PD6 with alternate functions ADC0 AIN6, AC0 P2, and CCL LUT2 OUT (alternate position).
17 PD7 bidirectional General-purpose I/O pin PD7 with alternate functions VREFA (external voltage reference), ADC0 AIN7, AC0 N2, and EVSYS EVOUTD (alternate position).
18 AVDD power_in Analog supply pin (AVDD) for the analog peripherals and the GPIO on the AVDD power domain; device supply range is 1.8-5.5 V per Ordering Information.
19 GND power_in Ground reference pin for the device.
20 PF0 bidirectional General-purpose I/O pin PF0 shared with the TOSC1 crystal oscillator input, with alternate functions USART2 TxD (alternate position), TCA0 WO0 (alternate position), and CCL LUT3 IN0.
21 PF1 bidirectional General-purpose I/O pin PF1 shared with the TOSC2 crystal oscillator output, with alternate functions USART2 RxD (alternate position), TCA0 WO1 (alternate position), and CCL LUT3 IN1.
22 PF2 bidirectional General-purpose I/O pin PF2 with alternate functions TWI0 SDA (client, alternate position), ADC0 AIN12, USART2 XCK, TCA0 WO2 (alternate position), EVSYS EVOUTF, and CCL LUT3 IN2.
23 PF3 bidirectional General-purpose I/O pin PF3 with alternate functions TWI0 SCL (client, alternate position), ADC0 AIN13, USART2 XDIR, TCA0 WO3 (alternate position), and CCL LUT3 OUT.
24 PF4 bidirectional General-purpose I/O pin PF4 with alternate functions ADC0 AIN14, USART2 TxD (alternate position), TCA0 WO4 (alternate position), and TCB0 WO (alternate position).
25 PF5 bidirectional General-purpose I/O pin PF5 with alternate functions ADC0 AIN15, USART2 RxD (alternate position), TCA0 WO5 (alternate position), and TCB1 WO (alternate position).
26 PF6 bidirectional Pin PF6 is the RESET pin when the RSTPINCFG fuse selects RESET (otherwise GPIO), with alternate functions USART2 XCK (alternate position) and CCL LUT3 OUT (alternate position).
27 UPDI bidirectional Unified Program and Debug Interface pin used for programming and debugging the device.
28 VDD power_in Digital supply pin for the device; supply range is 1.8-5.5 V per Ordering Information.
29 GND power_in Ground reference pin for the device.
30 PA0 bidirectional General-purpose I/O pin PA0 shared with the EXTCLK external clock input, with alternate functions USART0 TxD, TCA0 WO0, and CCL LUT0 IN0; it can be used as an event input and external interrupt source.
31 PA1 bidirectional General-purpose I/O pin PA1 with alternate functions USART0 RxD, TCA0 WO1, and CCL LUT0 IN1.
32 PA2 bidirectional General-purpose I/O pin PA2 with alternate functions TWI0 SDA (host), USART0 XCK, TCA0 WO2, TCB0 WO (default position), EVSYS EVOUTA, and CCL LUT0 IN2.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-32(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 32

CAD (KiCad official)

  • Symbol: ATMEGA808-AUR
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: atmega808-aur-etched.step / atmega808-aur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega808-aur.step / atmega808-aur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (552 pp, sha256 e4bbeee766cda6b4, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF