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ATMEGA64L-8MU

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Microchip Tech Pre-ordered MCUs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatmega64l-8mufactory-2.0.0extractor-text

Verified ATMEGA64L-8MU

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA64L-8MU · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 15-page datasheet
  • ✓distributor: lcsc C1340114, digikey ATMEGA64L-8MU-ND, mouser 556-ATMEGA64L-8MU
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-q2t5y5v5/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega64l-8mu.kicad_sym✓ atmega64l-8mu.kicad_mod✓ atmega64l-8mu.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers atmega64l-8mu: viewers · Ray 5d ago
atmega64l-8mu-etched.glb Publish 0.1.0 · Ray 5d ago
atmega64l-8mu-etched.step atmega64l-8mu: factory component page (tier=mfr) · Ray 5d ago
atmega64l-8mu-hero.glb atmega64l-8mu: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
atmega64l-8mu-hero.overlay.json Publish 0.1.0 · Ray 5d ago
atmega64l-8mu.glb Publish 0.1.0 · Ray 5d ago
atmega64l-8mu.kicad_mod Publish 0.1.0 · Ray 5d ago
atmega64l-8mu.kicad_sym Publish 0.1.0 · Ray 5d ago
atmega64l-8mu.lbr Publish 0.1.0 · Ray 5d ago
atmega64l-8mu.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 5d ago

ATMEGA64L-8MU

Microchip Tech · Pre-ordered MCUs · QFN-64-EP(9x9)

ATMEGA64L-8MU from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PEN input SPI Serial Programming enable pin, internally pulled high; holding it low during Power-on Reset enters SPI Serial Programming mode and it has no function during normal operation.
2 PE0 bidirectional Port E bit 0, bi-directional I/O with internal pull-up, alternate functions RXD0/(PDI).
3 PE1 bidirectional Port E bit 1, bi-directional I/O with internal pull-up, alternate functions (TXD0/PDO).
4 PE2 bidirectional Port E bit 2, bi-directional I/O with internal pull-up, alternate functions (XCK0/AIN0).
5 PE3 bidirectional Port E bit 3, bi-directional I/O with internal pull-up, alternate functions (OC3A/AIN1).
6 PE4 bidirectional Port E bit 4, bi-directional I/O with internal pull-up, alternate functions (OC3B/INT4).
7 PE5 bidirectional Port E bit 5, bi-directional I/O with internal pull-up, alternate functions (OC3C/INT5).
8 PE6 bidirectional Port E bit 6, bi-directional I/O with internal pull-up, alternate functions (T3/INT6).
9 PE7 bidirectional Port E bit 7, bi-directional I/O with internal pull-up, alternate functions (ICP3/INT7).
10 PB0 bidirectional Port B bit 0, bi-directional I/O with internal pull-up, alternate function (SS).
11 PB1 bidirectional Port B bit 1, bi-directional I/O with internal pull-up, alternate function (SCK).
12 PB2 bidirectional Port B bit 2, bi-directional I/O with internal pull-up, alternate function (MOSI).
13 PB3 bidirectional Port B bit 3, bi-directional I/O with internal pull-up, alternate function (MISO).
14 PB4 bidirectional Port B bit 4, bi-directional I/O with internal pull-up, alternate function (OC0).
15 PB5 bidirectional Port B bit 5, bi-directional I/O with internal pull-up, alternate function (OC1A).
16 PB6 bidirectional Port B bit 6, bi-directional I/O with internal pull-up, alternate function (OC1B).
17 PB7 bidirectional Port B bit 7, bi-directional I/O with internal pull-up, alternate functions (OC2/OC1C).
18 PG3/TOSC2 bidirectional Port G bit 3, bi-directional I/O with internal pull-up, also the TOSC2 real time counter oscillator pin.
19 PG4/TOSC1 bidirectional Port G bit 4, bi-directional I/O with internal pull-up, also the TOSC1 real time counter oscillator pin.
20 RESET input Reset input; a low level longer than the minimum pulse length generates a reset even if the clock is not running.
21 VCC power_in Digital supply voltage.
22 GND power_in Ground.
23 XTAL2 output Output from the inverting oscillator amplifier.
24 XTAL1 input Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
25 PD0 bidirectional Port D bit 0, bi-directional I/O with internal pull-up, alternate functions (SCL/INT0).
26 PD1 bidirectional Port D bit 1, bi-directional I/O with internal pull-up, alternate functions (SDA/INT1).
27 PD2 bidirectional Port D bit 2, bi-directional I/O with internal pull-up, alternate functions (RXD1/INT2).
28 PD3 bidirectional Port D bit 3, bi-directional I/O with internal pull-up, alternate functions (TXD1/INT3).
29 PD4 bidirectional Port D bit 4, bi-directional I/O with internal pull-up, alternate function (ICP1).
30 PD5 bidirectional Port D bit 5, bi-directional I/O with internal pull-up, alternate function (XCK1).
31 PD6 bidirectional Port D bit 6, bi-directional I/O with internal pull-up, alternate function (T1).
32 PD7 bidirectional Port D bit 7, bi-directional I/O with internal pull-up, alternate function (T2).
33 PG0 bidirectional Port G bit 0, bi-directional I/O with internal pull-up, external memory write strobe (WR).
34 PG1 bidirectional Port G bit 1, bi-directional I/O with internal pull-up, external memory read strobe (RD).
35 PC0 bidirectional Port C bit 0, bi-directional I/O with internal pull-up, external memory address A8.
36 PC1 bidirectional Port C bit 1, bi-directional I/O with internal pull-up, external memory address A9.
37 PC2 bidirectional Port C bit 2, bi-directional I/O with internal pull-up, external memory address A10.
38 PC3 bidirectional Port C bit 3, bi-directional I/O with internal pull-up, external memory address A11.
39 PC4 bidirectional Port C bit 4, bi-directional I/O with internal pull-up, external memory address A12.
40 PC5 bidirectional Port C bit 5, bi-directional I/O with internal pull-up, external memory address A13.
41 PC6 bidirectional Port C bit 6, bi-directional I/O with internal pull-up, external memory address A14.
42 PC7 bidirectional Port C bit 7, bi-directional I/O with internal pull-up, external memory address A15.
43 PG2 bidirectional Port G bit 2, bi-directional I/O with internal pull-up, external memory address latch enable (ALE).
44 PA7 bidirectional Port A bit 7, bi-directional I/O with internal pull-up, external memory address/data AD7.
45 PA6 bidirectional Port A bit 6, bi-directional I/O with internal pull-up, external memory address/data AD6.
46 PA5 bidirectional Port A bit 5, bi-directional I/O with internal pull-up, external memory address/data AD5.
47 PA4 bidirectional Port A bit 4, bi-directional I/O with internal pull-up, external memory address/data AD4.
48 PA3 bidirectional Port A bit 3, bi-directional I/O with internal pull-up, external memory address/data AD3.
49 PA2 bidirectional Port A bit 2, bi-directional I/O with internal pull-up, external memory address/data AD2.
50 PA1 bidirectional Port A bit 1, bi-directional I/O with internal pull-up, external memory address/data AD1.
51 PA0 bidirectional Port A bit 0, bi-directional I/O with internal pull-up, external memory address/data AD0.
52 VCC power_in Digital supply voltage.
53 GND power_in Ground.
54 PF7 bidirectional Port F bit 7, ADC7 analog input or I/O, JTAG TDI; its pull-up is activated when JTAG is enabled even during reset.
55 PF6 bidirectional Port F bit 6, ADC6 analog input or I/O, JTAG TDO, which is tri-stated unless TAP states that shift out data are entered.
56 PF5 bidirectional Port F bit 5, ADC5 analog input or I/O, JTAG TMS; its pull-up is activated when JTAG is enabled even during reset.
57 PF4 bidirectional Port F bit 4, ADC4 analog input or I/O, JTAG TCK; its pull-up is activated when JTAG is enabled even during reset.
58 PF3 bidirectional Port F bit 3, ADC3 analog input to the A/D Converter or general I/O.
59 PF2 bidirectional Port F bit 2, ADC2 analog input to the A/D Converter or general I/O.
60 PF1 bidirectional Port F bit 1, ADC1 analog input to the A/D Converter or general I/O.
61 PF0 bidirectional Port F bit 0, ADC0 analog input to the A/D Converter or general I/O.
62 AREF input Analog reference pin for the A/D Converter.
63 GND power_in Ground.
64 AVCC power_in Supply voltage pin for Port F and the A/D Converter; must be connected to VCC even if the ADC is not used, through a low-pass filter if the ADC is used.
65 EP power_in Exposed bottom pad of the QFN/MLF package, which should be soldered to ground.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Embedded Processors & Controllers
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VCC), ATmega64L speed grade 8 MHz VCC 2.7 5.5 V ATmega64L-8MU, 8 MHz speed grade (ordering table) 10
Speed grade (clock frequency), ATmega64L 0 8 MHz ATmega64L (features list; ordering table speed 8 MHz) 1
Operating temperature range, Industrial -40 85 °C Industrial operation range (-40C to 85C) for ATmega64L-8MU 10

CAD (KiCad official)

  • Symbol: ATMEGA64L-8MU
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: atmega64l-8mu-etched.step / atmega64l-8mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega64l-8mu.step / atmega64l-8mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (15 pp, sha256 0deef41350e65cc6, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF