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ATMEGA64A-MUR

Public Made by Adom

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleratmega64a-murfactory-2.0.0extractor-text

Verified ATMEGA64A-MUR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA64A-MUR · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C2053133, digikey ATMEGA64A-MURTR-ND, mouser 556-ATMEGA64A-MUR
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-nh_5nwp1/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.6)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega64a-mur.kicad_sym✓ atmega64a-mur.kicad_mod✓ atmega64a-mur.step
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Ray Publish 0.1.0 483feba 2d ago

ATMEGA64A-MUR

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-64-EP(9x9)

ATMEGA64A-MUR from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PEN input Programming enable pin for SPI Serial Programming mode, internally pulled high; holding it low during Power-on Reset enters SPI programming mode, no function in normal operation.
2 PE0 bidirectional Port E bit 0 bi-directional I/O with internal pull-up, alternate functions RXD0 (USART0 receive) and PDI (programming data in).
3 PE1 bidirectional Port E bit 1 bi-directional I/O with internal pull-up, alternate functions TXD0 (USART0 transmit) and PDO (programming data out).
4 PE2 bidirectional Port E bit 2 bi-directional I/O with internal pull-up, alternate functions XCK0 (USART0 clock) and AIN0 (analog comparator input).
5 PE3 bidirectional Port E bit 3 bi-directional I/O with internal pull-up, alternate functions OC3A and AIN1 (analog comparator input).
6 PE4 bidirectional Port E bit 4 bi-directional I/O with internal pull-up, alternate functions OC3B and INT4.
7 PE5 bidirectional Port E bit 5 bi-directional I/O with internal pull-up, alternate functions OC3C and INT5.
8 PE6 bidirectional Port E bit 6 bi-directional I/O with internal pull-up, alternate functions T3 and INT6.
9 PE7 bidirectional Port E bit 7 bi-directional I/O with internal pull-up, alternate functions ICP3 and INT7.
10 PB0 bidirectional Port B bit 0 bi-directional I/O with internal pull-up, alternate function SS (SPI slave select).
11 PB1 bidirectional Port B bit 1 bi-directional I/O with internal pull-up, alternate function SCK (SPI clock).
12 PB2 bidirectional Port B bit 2 bi-directional I/O with internal pull-up, alternate function MOSI (SPI).
13 PB3 bidirectional Port B bit 3 bi-directional I/O with internal pull-up, alternate function MISO (SPI).
14 PB4 bidirectional Port B bit 4 bi-directional I/O with internal pull-up, alternate function OC0.
15 PB5 bidirectional Port B bit 5 bi-directional I/O with internal pull-up, alternate function OC1A.
16 PB6 bidirectional Port B bit 6 bi-directional I/O with internal pull-up, alternate function OC1B.
17 PB7 bidirectional Port B bit 7 bi-directional I/O with internal pull-up, alternate functions OC2 and OC1C.
18 PG3 bidirectional Port G bit 3 bi-directional I/O with internal pull-up, alternate function TOSC2 (timer oscillator); PG3 and PG4 are oscillator pins in ATmega103 compatibility mode.
19 PG4 bidirectional Port G bit 4 bi-directional I/O with internal pull-up, alternate function TOSC1 (timer oscillator input).
20 RESET input Reset input; a low level longer than the minimum pulse length generates a reset even if the clock is not running.
21 VCC power_in Digital supply voltage.
22 GND power_in Ground.
23 XTAL2 output Output from the inverting oscillator amplifier.
24 XTAL1 input Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
25 PD0 bidirectional Port D bit 0 bi-directional I/O with internal pull-up, alternate functions SCL (TWI clock) and INT0.
26 PD1 bidirectional Port D bit 1 bi-directional I/O with internal pull-up, alternate functions SDA (TWI data) and INT1.
27 PD2 bidirectional Port D bit 2 bi-directional I/O with internal pull-up, alternate functions RXD1 (USART1 receive) and INT2.
28 PD3 bidirectional Port D bit 3 bi-directional I/O with internal pull-up, alternate functions TXD1 (USART1 transmit) and INT3.
29 PD4 bidirectional Port D bit 4 bi-directional I/O with internal pull-up, alternate function ICP1.
30 PD5 bidirectional Port D bit 5 bi-directional I/O with internal pull-up, alternate function XCK1 (USART1 clock).
31 PD6 bidirectional Port D bit 6 bi-directional I/O with internal pull-up, alternate function T1.
32 PD7 bidirectional Port D bit 7 bi-directional I/O with internal pull-up, alternate function T2.
33 PG0 bidirectional Port G bit 0 bi-directional I/O with internal pull-up, alternate function WR (external memory write strobe).
34 PG1 bidirectional Port G bit 1 bi-directional I/O with internal pull-up, alternate function RD (external memory read strobe).
35 PC0 bidirectional Port C bit 0 bi-directional I/O with internal pull-up, alternate function A8 (external memory address).
36 PC1 bidirectional Port C bit 1 bi-directional I/O with internal pull-up, alternate function A9 (external memory address).
37 PC2 bidirectional Port C bit 2 bi-directional I/O with internal pull-up, alternate function A10 (external memory address).
38 PC3 bidirectional Port C bit 3 bi-directional I/O with internal pull-up, alternate function A11 (external memory address).
39 PC4 bidirectional Port C bit 4 bi-directional I/O with internal pull-up, alternate function A12 (external memory address).
40 PC5 bidirectional Port C bit 5 bi-directional I/O with internal pull-up, alternate function A13 (external memory address).
41 PC6 bidirectional Port C bit 6 bi-directional I/O with internal pull-up, alternate function A14 (external memory address).
42 PC7 bidirectional Port C bit 7 bi-directional I/O with internal pull-up, alternate function A15 (external memory address).
43 PG2 bidirectional Port G bit 2 bi-directional I/O with internal pull-up, alternate function ALE (external memory address latch enable).
44 PA7 bidirectional Port A bit 7 bi-directional I/O with internal pull-up, alternate function AD7 (external memory address/data).
45 PA6 bidirectional Port A bit 6 bi-directional I/O with internal pull-up, alternate function AD6 (external memory address/data).
46 PA5 bidirectional Port A bit 5 bi-directional I/O with internal pull-up, alternate function AD5 (external memory address/data).
47 PA4 bidirectional Port A bit 4 bi-directional I/O with internal pull-up, alternate function AD4 (external memory address/data).
48 PA3 bidirectional Port A bit 3 bi-directional I/O with internal pull-up, alternate function AD3 (external memory address/data).
49 PA2 bidirectional Port A bit 2 bi-directional I/O with internal pull-up, alternate function AD2 (external memory address/data).
50 PA1 bidirectional Port A bit 1 bi-directional I/O with internal pull-up, alternate function AD1 (external memory address/data).
51 PA0 bidirectional Port A bit 0 bi-directional I/O with internal pull-up, alternate function AD0 (external memory address/data).
52 VCC power_in Digital supply voltage.
53 GND power_in Ground.
54 PF7 bidirectional Port F bit 7, ADC7 analog input to the A/D Converter or I/O, also JTAG TDI with pull-up active when JTAG is enabled.
55 PF6 bidirectional Port F bit 6, ADC6 analog input to the A/D Converter or I/O, also JTAG TDO (tri-stated unless TAP states shift out data).
56 PF5 bidirectional Port F bit 5, ADC5 analog input to the A/D Converter or I/O, also JTAG TMS with pull-up active when JTAG is enabled.
57 PF4 bidirectional Port F bit 4, ADC4 analog input to the A/D Converter or I/O, also JTAG TCK with pull-up active when JTAG is enabled.
58 PF3 bidirectional Port F bit 3, ADC3 analog input to the A/D Converter or general I/O.
59 PF2 bidirectional Port F bit 2, ADC2 analog input to the A/D Converter or general I/O.
60 PF1 bidirectional Port F bit 1, ADC1 analog input to the A/D Converter or general I/O.
61 PF0 bidirectional Port F bit 0, ADC0 analog input to the A/D Converter or general I/O.
62 AREF input Analog reference pin for the A/D Converter.
63 GND power_in Ground.
64 AVCC power_in Supply voltage for Port F and the A/D Converter; must be connected to VCC even if the ADC is unused, through a low-pass filter if the ADC is used.
65 EP power_in Exposed bottom pad of the QFN/MLF package, which should be soldered to ground.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Single Chip Microcomputer/Microcontroller
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage VCC 2.7 5.5 V 5
Speed grade / operating frequency 0 16 MHz Speed grade, 2.7 - 5.5V 6
Operating temperature, Industrial (ATmega64A-MUR) -40 85 °C Industrial operational range 6
RC Oscillator tolerance -3 3 % 5
AC propagation delay 400 ns Typ 5

CAD (KiCad official)

  • Symbol: ATMEGA64A-MUR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: atmega64a-mur-etched.step / atmega64a-mur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega64a-mur.step / atmega64a-mur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (20 pp, sha256 0a4e7cc14d7f3fdb, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF