Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	7d ago
viewers	atmega64-16au: viewers · Ray	7d ago
atmega64-16au-etched.glb	Publish 0.1.0 · Ray	7d ago
atmega64-16au-etched.step	atmega64-16au: factory component page (tier=mfr) · Ray	7d ago
atmega64-16au-hero.glb	atmega64-16au: hero GLB from the etched model (keeps the MPN mark) · Ray	7d ago
atmega64-16au-hero.overlay.json	Publish 0.1.0 · Ray	7d ago
atmega64-16au.glb	Publish 0.1.0 · Ray	7d ago
atmega64-16au.kicad_mod	Publish 0.1.0 · Ray	7d ago
atmega64-16au.kicad_sym	Publish 0.1.0 · Ray	7d ago
atmega64-16au.lbr	Publish 0.1.0 · Ray	7d ago
atmega64-16au.step	Publish 0.1.0 · Ray	7d ago
package.json	Publish 0.1.0 · Ray	7d ago
page.json	Set visibility: public · Ray	7d ago
README.md	Publish 0.1.0 · Ray	7d ago

ATMEGA64-16AU

Microchip Tech · MICROCHIP · TQFP-64(14x14)

ATMEGA64-16AU from Microchip Tech, in a TQFP-64(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PEN	input	Programming enable pin for SPI Serial Programming mode; holding it low during a Power-on Reset enters that mode, it is internally pulled high, and it has no function during normal operation.
2	PE0	bidirectional	Port E bit 0 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves RXD0/(PDI).
3	PE1	bidirectional	Port E bit 1 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves TXD0/(PDO).
4	PE2	bidirectional	Port E bit 2 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves XCK0/AIN0.
5	PE3	bidirectional	Port E bit 3 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves OC3A/AIN1.
6	PE4	bidirectional	Port E bit 4 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves OC3B/INT4.
7	PE5	bidirectional	Port E bit 5 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves OC3C/INT5.
8	PE6	bidirectional	Port E bit 6 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves T3/INT6.
9	PE7	bidirectional	Port E bit 7 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves ICP3/INT7.
10	PB0	bidirectional	Port B bit 0 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves SS.
11	PB1	bidirectional	Port B bit 1 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves SCK.
12	PB2	bidirectional	Port B bit 2 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves MOSI.
13	PB3	bidirectional	Port B bit 3 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves MISO.
14	PB4	bidirectional	Port B bit 4 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves OC0.
15	PB5	bidirectional	Port B bit 5 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves OC1A.
16	PB6	bidirectional	Port B bit 6 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves OC1B.
17	PB7	bidirectional	Port B bit 7 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves OC2/OC1C.
18	PG3	bidirectional	Port G bit 3 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it is the TOSC2 Oscillator pin.
19	PG4	bidirectional	Port G bit 4 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it is the TOSC1 Oscillator pin.
20	RESET	input	Reset input; a low level on this pin for longer than the minimum pulse length (Table 19, page 52) generates a reset even if the clock is not running, and shorter pulses are not guaranteed to reset the device.
21	VCC	power_in	Digital supply voltage.
22	GND	power_in	Ground.
23	XTAL2	output	Output from the inverting Oscillator amplifier.
24	XTAL1	input	Input to the inverting Oscillator amplifier and to the internal clock operating circuit.
25	PD0	bidirectional	Port D bit 0 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves SCL/INT0.
26	PD1	bidirectional	Port D bit 1 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves SDA/INT1.
27	PD2	bidirectional	Port D bit 2 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves RXD1/INT2.
28	PD3	bidirectional	Port D bit 3 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves TXD1/INT3.
29	PD4	bidirectional	Port D bit 4 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves ICP1.
30	PD5	bidirectional	Port D bit 5 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves XCK1.
31	PD6	bidirectional	Port D bit 6 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves T1.
32	PD7	bidirectional	Port D bit 7 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves T2.
33	PG0	bidirectional	Port G bit 0 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves the WR external memory strobe.
34	PG1	bidirectional	Port G bit 1 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves the RD external memory strobe.
35	PC0	bidirectional	Port C bit 0 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A8.
36	PC1	bidirectional	Port C bit 1 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A9.
37	PC2	bidirectional	Port C bit 2 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A10.
38	PC3	bidirectional	Port C bit 3 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A11.
39	PC4	bidirectional	Port C bit 4 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A12.
40	PC5	bidirectional	Port C bit 5 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A13.
41	PC6	bidirectional	Port C bit 6 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A14.
42	PC7	bidirectional	Port C bit 7 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves address line A15.
43	PG2	bidirectional	Port G bit 2 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves the ALE external memory strobe.
44	PA7	bidirectional	Port A bit 7 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD7.
45	PA6	bidirectional	Port A bit 6 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD6.
46	PA5	bidirectional	Port A bit 5 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD5.
47	PA4	bidirectional	Port A bit 4 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD4.
48	PA3	bidirectional	Port A bit 3 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD3.
49	PA2	bidirectional	Port A bit 2 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD2.
50	PA1	bidirectional	Port A bit 1 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD1.
51	PA0	bidirectional	Port A bit 0 is a bi-directional I/O pin with selectable internal pull-up, tri-stated when reset is active; it also serves AD0.
52	VCC	power_in	Digital supply voltage.
53	GND	power_in	Ground.
54	PF7	bidirectional	Port F bit 7 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin with selectable pull-up; it also serves ADC7/TDI, and its pull-up stays active during reset while JTAG is enabled.
55	PF6	bidirectional	Port F bit 6 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin; it also serves ADC6/TDO, which is tri-stated unless TAP states that shift out data are entered.
56	PF5	bidirectional	Port F bit 5 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin; it also serves ADC5/TMS, and its pull-up stays active during reset while JTAG is enabled.
57	PF4	bidirectional	Port F bit 4 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin; it also serves ADC4/TCK, and its pull-up stays active during reset while JTAG is enabled.
58	PF3	bidirectional	Port F bit 3 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin with selectable pull-up; it also serves ADC3.
59	PF2	bidirectional	Port F bit 2 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin with selectable pull-up; it also serves ADC2.
60	PF1	bidirectional	Port F bit 1 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin with selectable pull-up; it also serves ADC1.
61	PF0	bidirectional	Port F bit 0 serves as an ADC analog input and, when the A/D Converter is unused, as an I/O pin with selectable pull-up; it also serves ADC0.
62	AREF	input	Analog reference pin for the A/D Converter.
63	GND	power_in	Ground.
64	AVCC	power_in	Supply voltage pin for Port F and the A/D Converter; it should be externally connected to VCC even if the ADC is not used, and through a low-pass filter if the ADC is used.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	TQFP-64(14x14)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Min	Max	Unit	Conditions	Page
Speed grade (clock frequency range)	0	16	MHz	ATmega64 (16 MHz speed grade)	1
Power supply voltage (ATmega64-16AU, 16 MHz grade)	4.5	5.5	V	ATmega64-16AU, speed 16 MHz	10
Operating temperature range (Industrial)	-40	85	°C	Industrial operation range, ATmega64-16AU	10

CAD (KiCad official)

Symbol: ATMEGA64-16AU
Footprint: Package_QFP:TQFP-64_14x14mm_P0.8mm
3D model: TQFP-64(14x14) (KiCad packages3D, STEP)
3D model files: atmega64-16au-etched.step / atmega64-16au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega64-16au.step / atmega64-16au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (15 pp, sha256 0deef41350e65cc6, retrieved 2026-10-29, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF