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ATMEGA48PA-MUR

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ATMEGA48PA-MUR

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)

ATMEGA48PA-MUR from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD3 bidirectional Port D bit 3 that can serve as external interrupt 1 input (INT1) or as the OC2B Timer/Counter2 compare output, which requires the pin to be configured as an output.
2 PD4 bidirectional Port D bit 4 that can serve as the USART external clock (XCK) or the Timer/Counter0 external counter input (T0).
3 GND power_in Ground.
4 VCC power_in Digital supply voltage.
5 GND power_in Ground.
6 VCC power_in Digital supply voltage.
7 PB6 input Chip clock oscillator pin 1 (XTAL1) or timer oscillator pin 1 (TOSC1), which cannot be used as an I/O pin when used as a clock pin.
8 PB7 output Chip clock oscillator pin 2 (XTAL2) driven as the output of the inverting oscillator amplifier, which cannot be used as an I/O pin when used as a clock pin.
9 PD5 bidirectional Port D bit 5 that can serve as the Timer/Counter1 external counter input (T1) or as the OC0B Timer/Counter0 compare output, which requires the pin to be configured as an output.
10 PD6 bidirectional Port D bit 6 that can serve as the analog comparator positive input (AIN0) or as the OC0A Timer/Counter0 compare output, which requires the pin to be configured as an output.
11 PD7 bidirectional Port D bit 7 that serves as the analog comparator negative input (AIN1), for which the pin should be configured as input with the internal pull-up switched off.
12 PB0 bidirectional Port B bit 0 that can serve as the Timer/Counter1 input capture pin (ICP1) or as the divided system clock output (CLKO) when the CKOUT fuse is programmed.
13 PB1 bidirectional Port B bit 1 that serves as the Timer/Counter1 output compare match A output (OC1A), which requires the pin to be configured as an output.
14 PB2 bidirectional Port B bit 2 that serves as the SPI slave select input (SS) or as the Timer/Counter1 output compare match B output (OC1B), which requires the pin to be configured as an output.
15 PB3 bidirectional Port B bit 3 that serves as the SPI master output/slave input (MOSI) or as the Timer/Counter2 output compare match A output (OC2A), which requires the pin to be configured as an output.
16 PB4 bidirectional Port B bit 4 that serves as the SPI master input/slave output (MISO) pin.
17 PB5 bidirectional Port B bit 5 that serves as the SPI clock pin (SCK), an input when the SPI is a slave and controlled by DDB5 when the SPI is a master.
18 AVCC power_in Supply voltage pin for the A/D converter, PC3:0 and ADC7:6, which should be connected to VCC even if the ADC is not used and through a low-pass filter if it is.
19 ADC6 passive Analog input channel 6 of the 10-bit A/D converter, powered from the analog supply (TQFP and QFN package only).
20 AREF input Analog reference pin for the A/D converter.
21 GND power_in Ground.
22 ADC7 passive Analog input channel 7 of the 10-bit A/D converter, powered from the analog supply (TQFP and QFN package only).
23 PC0 bidirectional Port C bit 0 that can also serve as ADC input channel 0, which uses analog power, and as pin change interrupt source 8.
24 PC1 bidirectional Port C bit 1 that can also serve as ADC input channel 1, which uses analog power, and as pin change interrupt source 9.
25 PC2 bidirectional Port C bit 2 that can also serve as ADC input channel 2, which uses analog power, and as pin change interrupt source 10.
26 PC3 bidirectional Port C bit 3 that can also serve as ADC input channel 3, which uses analog power, and as pin change interrupt source 11.
27 PC4 bidirectional Port C bit 4 that serves as the 2-wire serial interface data I/O (SDA) when TWEN is set, and as ADC input channel 4 which uses digital power.
28 PC5 bidirectional Port C bit 5 that serves as the 2-wire serial interface clock I/O (SCL) when TWEN is set, and as ADC input channel 5 which uses digital power.
29 PC6/RESET input Reset input when the RSTDISBL fuse is unprogrammed, where a low level longer than the minimum pulse length (Table 29-5) generates a reset; if the RSTDISBL fuse is programmed it functions as a normal I/O pin.
30 PD0 bidirectional Port D bit 0 that serves as the USART receive data input (RXD), configured as an input when the USART receiver is enabled.
31 PD1 bidirectional Port D bit 1 that serves as the USART transmit data output (TXD), configured as an output when the USART transmitter is enabled.
32 PD2 bidirectional Port D bit 2 that can serve as external interrupt source 0 (INT0) and as pin change interrupt source 18.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-32-EP(5x5)
Category Single Chip Microcomputer/Microcontroller
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature -55 125 °C 268
Storage temperature -65 150 °C 268
Voltage on any pin except RESET with respect to ground -0.5 V 268
Voltage on RESET with respect to ground -0.5 13 V 268
Maximum operating voltage 6 V 268
DC current per I/O pin 40 mA 268
DC current VCC and GND pins 200 mA 268
Input low voltage, except XTAL1 and RESET pin VIL -0.3 V VCC = 2.7V - 5.5V 269
Input low voltage, XTAL1 pin VIL1 -0.3 V VCC = 2.7V - 5.5V 269
Input low voltage, RESET pin VIL2 -0.3 V VCC = 2.7V - 5.5V 269
Output low voltage except RESET pin VOL 0.8 V IOL = 20mA, VCC = 5V 269
Output low voltage except RESET pin VOL 0.5 V IOL = 5mA, VCC = 3V 269
Output high voltage except reset pin VOH 4.1 V IOH = -20mA, VCC = 5V 269
Output high voltage except reset pin VOH 2.3 V IOH = -10mA, VCC = 3V 269
Input leakage current I/O pin (absolute value) IIL 1 µA VCC = 5.5V, pin low 269
Reset Pull-up Resistor RRST 30 60 k VCC = 5V, Vin = 0V 269
I/O pin pull-up resistor RPU 20 50 k 269
Analog comparator input offset voltage VACIO 40 mV VCC = 5V, 0.1VCC < Vin < VCC - 100mV 269
Analog comparator input leakage current IACLK -50 50 nA 0.1VCC < Vin < VCC, 100mV 269
Analog comparator propagation delay tACID 140 ns VCC = 4.5V 269
Power Supply Current Active 4MHz ICC 1.3 2.4 mA Active 4MHz, VCC = 3V 270
Power Supply Current Active 8MHz ICC 4.6 10 mA Active 8MHz, VCC = 5V 270
Power Supply Current Active 16MHz ICC 8.4 16 mA Active 16MHz, VCC = 5V 270
Power Supply Current Idle 4MHz ICC 0.2 0.6 mA Idle 4MHz, VCC = 3V 270
Power Supply Current Idle 8MHz ICC 0.9 1.6 mA Idle 8MHz, VCC = 5V 270
Power Supply Current Idle 16MHz ICC 1.8 4 mA Idle 16MHz, VCC = 5V 270
Power-down mode current 4.2 44 µA WDT enabled, VCC = 3V 270
Power-down mode current 6.2 66 µA WDT enabled, VCC = 5V 270
Power-down mode current 0.8 40 µA WDT disabled, VCC = 3V 270
Power-down mode current 1.1 60 µA WDT disabled, VCC = 5V 270
Calibrated internal RC oscillator accuracy (factory calibration) -1 1 % 8.0MHz, 3V, 25°C, default factory calibration 271
Calibrated internal RC oscillator accuracy -14 14 % 8.0MHz, VCC 2.7V to 5.5V, -40°C to 125°C 271
Calibrated internal RC oscillator accuracy -10 10 % 8.0MHz, VCC 4.5V to 5.5V, -40°C to 125°C 271
Watchdog oscillator accuracy -40 40 % 128kHz, VCC 2.7V to 5.5V, -40°C to 125°C 271
Oscillator frequency 1/tCLCL 0 8 MHz VCC = 2.7 - 5.5V 271
Oscillator frequency 1/tCLCL 0 16 MHz VCC = 4.5 - 5.5V 271
Clock period tCLCL 125 ns VCC = 2.7 - 5.5V 271
Clock period tCLCL 62.5 ns VCC = 4.5 - 5.5V 271
High time tCHCX 50 ns VCC = 2.7 - 5.5V 271
High time tCHCX 25 ns VCC = 4.5 - 5.5V 271
Low time tCLCX 50 ns VCC = 2.7 - 5.5V 271
Low time tCLCX 25 ns VCC = 4.5 - 5.5V 271
Rise time tCLCH 1.6 µs VCC = 2.7 - 5.5V 271
Rise time tCLCH 0.5 µs VCC = 4.5 - 5.5V 271
Fall time tCHCL 1.6 µs VCC = 2.7 - 5.5V 271
Fall time tCHCL 0.5 µs VCC = 4.5 - 5.5V 271
Power-on reset threshold voltage (rising) VPOT 1.4 V 272
Power-on reset threshold voltage (falling) VPOT 0.6 1.3 1.6 V 272
VCC maximum start voltage to ensure internal power-on reset signal Vpormax 0.4 V 272
VCC minimum start voltage to ensure internal power-on reset signal Vpormin -0.1 V 272
VCC rise rate to ensure power-on reset VCCRR 0.01 V/ms 272
Minimum pulse width on RESET pin tRST 2.5 µs 272
Bandgap reference voltage VBG 1 1.1 1.2 V 272
Brown-out reset threshold VBOT (BODLEVEL 110) VBOT 1.6 1.8 2 V BODLEVEL 2:0 = 110 272
Brown-out reset threshold VBOT (BODLEVEL 101) VBOT 2.5 2.7 2.9 V BODLEVEL 2:0 = 101 272
Brown-out reset threshold VBOT (BODLEVEL 100) VBOT 3.9 4.3 4.6 V BODLEVEL 2:0 = 100 272
SCL clock frequency fSCL 0 400 kHz fCK > max(16fSCL, 250kHz) 275
Rise time for both SDA and SCL tr 300 ns 275

CAD (KiCad official)

  • Symbol: ATMEGA48PA-MUR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: atmega48pa-mur-etched.step / atmega48pa-mur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega48pa-mur.step / atmega48pa-mur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (326 pp, sha256 626d81e6d4d566ae, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF