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ATMEGA48PA-MU
Public Made by Adomby adom
Microchip Tech MICROCHIP, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
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| docs | 7d ago |
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| atmega48pa-mu-etched.glb | 7d ago |
| atmega48pa-mu-etched.step | 7d ago |
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| atmega48pa-mu-hero.overlay.json | 7d ago |
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ATMEGA48PA-MU
Microchip Tech · MICROCHIP · VQFN-32(5x5)
ATMEGA48PA-MU from Microchip Tech, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD3 | bidirectional | Port D bit 3 is a bidirectional I/O pin with internal pull-up; its alternate functions are INT1 external interrupt 1 input, OC2B Timer/Counter2 compare match B output, and PCINT19. |
| 2 | PD4 | bidirectional | Port D bit 4 is a bidirectional I/O pin with internal pull-up; its alternate functions are XCK USART external clock, T0 Timer/Counter0 external counter input, and PCINT20. |
| 3 | GND | power_in | Ground. |
| 4 | VCC | power_in | Digital supply voltage; the datasheet operating voltage range is 2.7V to 5.5V. |
| 5 | GND | power_in | Ground. |
| 6 | VCC | power_in | Digital supply voltage; the datasheet operating voltage range is 2.7V to 5.5V. |
| 7 | PB6 | bidirectional | Port B bit 6 is used as XTAL1/TOSC1 (chip clock oscillator pin 1 or external clock input, or timer oscillator input) depending on fuse and ASSR settings, otherwise a bidirectional I/O pin; it can also serve as PCINT6, and it cannot be used as I/O when used as a clock pin. |
| 8 | PB7 | bidirectional | Port B bit 7 is used as XTAL2/TOSC2 (output of the inverting oscillator amplifier or timer oscillator pin 2) depending on fuse and ASSR settings, otherwise a bidirectional I/O pin; it can also serve as PCINT7, and it cannot be used as I/O when used as a clock pin. |
| 9 | PD5 | bidirectional | Port D bit 5 is a bidirectional I/O pin with internal pull-up; its alternate functions are T1 Timer/Counter1 external counter input, OC0B Timer/Counter0 compare match B output, and PCINT21. |
| 10 | PD6 | bidirectional | Port D bit 6 is a bidirectional I/O pin with internal pull-up; its alternate functions are AIN0 analog comparator positive input (pull-up should be disabled), OC0A Timer/Counter0 compare match A output, and PCINT22. |
| 11 | PD7 | bidirectional | Port D bit 7 is a bidirectional I/O pin with internal pull-up; its alternate functions are AIN1 analog comparator negative input (pull-up should be disabled), and PCINT23. |
| 12 | PB0 | bidirectional | Port B bit 0 is a bidirectional I/O pin with internal pull-up; its alternate functions are ICP1 Timer/Counter1 input capture input, CLKO divided system clock output, and PCINT0. |
| 13 | PB1 | bidirectional | Port B bit 1 is a bidirectional I/O pin with internal pull-up; its alternate functions are OC1A Timer/Counter1 compare match A output (must be configured as output) and PCINT1. |
| 14 | PB2 | bidirectional | Port B bit 2 is a bidirectional I/O pin with internal pull-up; its alternate functions are SS SPI slave select input, OC1B Timer/Counter1 compare match B output (must be configured as output), and PCINT2. |
| 15 | PB3 | bidirectional | Port B bit 3 is a bidirectional I/O pin with internal pull-up; its alternate functions are MOSI SPI master output/slave input, OC2A Timer/Counter2 compare match A output (must be configured as output), and PCINT3. |
| 16 | PB4 | bidirectional | Port B bit 4 is a bidirectional I/O pin with internal pull-up; its alternate functions are MISO SPI master input/slave output and PCINT4. |
| 17 | PB5 | bidirectional | Port B bit 5 is a bidirectional I/O pin with internal pull-up; its alternate functions are SCK SPI clock (master output or slave input) and PCINT5. |
| 18 | AVCC | power_in | Supply voltage pin for the A/D converter, PC3:0 and ADC7:6; it should be connected to VCC even if the ADC is not used, and through a low-pass filter if the ADC is used. |
| 19 | ADC6 | input | Analog input to the 10-bit A/D converter (channel 6), powered from the analog supply; available in the QFN and TQFP packages only. |
| 20 | AREF | input | Analog reference pin for the A/D converter. |
| 21 | GND | power_in | Ground. |
| 22 | ADC7 | input | Analog input to the 10-bit A/D converter (channel 7), powered from the analog supply; available in the QFN and TQFP packages only. |
| 23 | PC0 | bidirectional | Port C bit 0 is a bidirectional I/O pin with internal pull-up; it is also ADC input channel 0 (uses analog power) and PCINT8. |
| 24 | PC1 | bidirectional | Port C bit 1 is a bidirectional I/O pin with internal pull-up; it is also ADC input channel 1 (uses analog power) and PCINT9. |
| 25 | PC2 | bidirectional | Port C bit 2 is a bidirectional I/O pin with internal pull-up; it is also ADC input channel 2 (uses analog power) and PCINT10. |
| 26 | PC3 | bidirectional | Port C bit 3 is a bidirectional I/O pin with internal pull-up; it is also ADC input channel 3 (uses analog power) and PCINT11. |
| 27 | PC4 | bidirectional | Port C bit 4 is a bidirectional I/O pin with internal pull-up; it is also SDA 2-wire serial data I/O when TWI is enabled, ADC input channel 4 (uses digital power), and PCINT12. |
| 28 | PC5 | bidirectional | Port C bit 5 is a bidirectional I/O pin with internal pull-up; it is also SCL 2-wire serial clock I/O when TWI is enabled, ADC input channel 5 (uses digital power), and PCINT13. |
| 29 | PC6 | input | Reset input when the RSTDISBL fuse is unprogrammed (a low level longer than the minimum pulse length generates a reset); when RSTDISBL is programmed it is a general I/O pin, and it also serves as PCINT14. |
| 30 | PD0 | bidirectional | Port D bit 0 is a bidirectional I/O pin with internal pull-up; it is also RXD USART receive data input (configured as input when the USART receiver is enabled) and PCINT16. |
| 31 | PD1 | bidirectional | Port D bit 1 is a bidirectional I/O pin with internal pull-up; it is also TXD USART transmit data output (configured as output when the USART transmitter is enabled) and PCINT17. |
| 32 | PD2 | bidirectional | Port D bit 2 is a bidirectional I/O pin with internal pull-up; it is also INT0 external interrupt 0 input and PCINT18. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-32(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature | -55 | 125 | °C | 268 | |||
| Storage temperature | -65 | 150 | °C | 268 | |||
| Voltage on any pin except RESET with respect to ground | -0.5 | V | with respect to ground | 268 | |||
| Voltage on RESET with respect to ground | -0.5 | 13 | V | with respect to ground | 268 | ||
| Maximum operating voltage | 6 | V | 268 | ||||
| DC current per I/O pin | 40 | mA | 268 | ||||
| DC current VCC and GND pins | 200 | mA | 268 | ||||
| Supply voltage VCC | VCC | 2.7 | 5.5 | V | TA = -40°C to 125°C | 269 | |
| Input low voltage, except XTAL1 and RESET pin | VIL | -0.3 | V | VCC = 2.7V - 5.5V | 269 | ||
| Input low voltage, XTAL1 pin | VIL1 | -0.3 | V | VCC = 2.7V - 5.5V | 269 | ||
| Input low voltage, RESET pin | VIL2 | -0.3 | V | VCC = 2.7V - 5.5V | 269 | ||
| Output low voltage (except RESET pin) | VOL | 0.8 | V | IOL = 20mA, VCC = 5V | 269 | ||
| Output low voltage (except RESET pin) | VOL | 0.5 | V | IOL = 5mA, VCC = 3V | 269 | ||
| Output high voltage (except reset pin) | VOH | 4.1 | V | IOH = -20mA, VCC = 5V | 269 | ||
| Output high voltage (except reset pin) | VOH | 2.3 | V | IOH = -10mA, VCC = 3V | 269 | ||
| Input leakage current I/O pin (pin low, absolute value) | IIL | 1 | µA | VCC = 5.5V, pin low (absolute value) | 269 | ||
| Input leakage current I/O pin (pin high, absolute value) | IIH | 1 | µA | VCC = 5.5V, pin high (absolute value) | 269 | ||
| Reset pull-up resistor | RRST | 30 | 60 | k | VCC = 5V, Vin = 0V | 269 | |
| I/O pin pull-up resistor | RPU | 20 | 50 | k | 269 | ||
| Analog comparator input offset voltage | VACIO | 10 | 40 | mV | VCC = 5V, 0.1VCC < Vin < VCC, 100mV | 269 | |
| Analog comparator input leakage current | IACLK | -50 | 50 | nA | 0.1VCC < Vin < VCC, 100mV | 269 | |
| Power supply current, active 4MHz | ICC | 1.3 | 2.4 | mA | Active 4MHz, VCC = 3V | 270 | |
| Power supply current, active 8MHz | ICC | 4.6 | 10 | mA | Active 8MHz, VCC = 5V | 270 | |
| Power supply current, active 16MHz | ICC | 8.4 | 16 | mA | Active 16MHz, VCC = 5V | 270 | |
| Power supply current, idle 4MHz | ICC | 0.2 | 0.6 | mA | Idle 4MHz, VCC = 3V | 270 | |
| Power supply current, idle 8MHz | ICC | 0.9 | 1.6 | mA | Idle 8MHz, VCC = 5V | 270 | |
| Power supply current, idle 16MHz | ICC | 1.8 | 4 | mA | Idle 16MHz, VCC = 5V | 270 | |
| Power supply current, power-down, WDT enabled | ICC | 4.2 | 44 | µA | WDT enabled, VCC = 3V | 270 | |
| Power supply current, power-down, WDT enabled | ICC | 6.2 | 66 | µA | WDT enabled, VCC = 5V | 270 | |
| Power supply current, power-down, WDT disabled | ICC | 0.8 | 40 | µA | WDT disabled, VCC = 3V | 270 | |
| Power supply current, power-down, WDT disabled | ICC | 1.1 | 60 | µA | WDT disabled, VCC = 5V | 270 | |
| Calibrated internal RC oscillator accuracy (factory calibration) | -1 | 1 | % | Factory calibration 8.0MHz, 3V, 25°C | 271 | ||
| Calibrated internal RC oscillator accuracy (factory calibration) | -14 | 14 | % | VCC 2.7V to 5.5V, -40°C to 125°C | 271 | ||
| Calibrated internal RC oscillator accuracy (factory calibration) | -10 | 10 | % | VCC 4.5V to 5.5V, -40°C to 125°C | 271 | ||
| Watchdog oscillator accuracy (128kHz) | -40 | 40 | % | VCC 2.7V to 5.5V, -40°C to 125°C | 271 | ||
| Oscillator frequency (external clock) | 1/tCLCL | 0 | 8 | MHz | VCC = 2.7 - 5.5V | 271 | |
| Oscillator frequency (external clock) | 1/tCLCL | 0 | 16 | MHz | VCC = 4.5 - 5.5V | 271 | |
| High time (external clock) | tCHCX | 50 | ns | VCC = 2.7 - 5.5V | 271 | ||
| High time (external clock) | tCHCX | 25 | ns | VCC = 4.5 - 5.5V | 271 | ||
| Low time (external clock) | tCLCX | 50 | ns | VCC = 2.7 - 5.5V | 271 | ||
| Low time (external clock) | tCLCX | 25 | ns | VCC = 4.5 - 5.5V | 271 | ||
| Rise time (external clock) | tCLCH | 1.6 | µs | VCC = 2.7 - 5.5V | 271 | ||
| Rise time (external clock) | tCLCH | 0.5 | µs | VCC = 4.5 - 5.5V | 271 | ||
| Fall time (external clock) | tCHCL | 1.6 | µs | VCC = 2.7 - 5.5V | 271 | ||
| Fall time (external clock) | tCHCL | 0.5 | µs | VCC = 4.5 - 5.5V | 271 | ||
| Power-on reset threshold voltage (falling) | VPOT | 0.6 | 1.3 | 1.6 | V | 272 | |
| VCC maximum start voltage to ensure internal power-on reset signal | Vpormax | 0.4 | V | 272 | |||
| VCC minimum start voltage to ensure internal power-on reset signal | Vpormin | -0.1 | V | 272 | |||
| Minimum pulse width on RESET pin | tRST | 2.5 | µs | 272 | |||
| Bandgap reference voltage | VBG | 1 | 1.1 | 1.2 | V | 272 | |
| Brown-out detection voltage VBOT (BODLEVEL 110) | VBOT | 1.6 | 1.8 | 2 | V | BODLEVEL[2:0] = 110 | 272 |
| Brown-out detection voltage VBOT (BODLEVEL 101) | VBOT | 2.5 | 2.7 | 2.9 | V | BODLEVEL[2:0] = 101 | 272 |
| Brown-out detection voltage VBOT (BODLEVEL 100) | VBOT | 3.9 | 4.3 | 4.6 | V | BODLEVEL[2:0] = 100 | 272 |
| Absolute accuracy (ADC) | TUE | 2.2 | 3.5 | LSB | VCC = 4V, VREF = 4V | 276 | |
| Integral non-linearity (ADC) | INL | 0.6 | 1.5 | LSB | VCC = 4V, VREF = 4V | 276 | |
| Differential non-linearity (ADC) | DNL | 0.3 | 0.7 | LSB | VCC = 4V, VREF = 4V | 276 | |
| Gain error (ADC) | -4 | 3 | LSB | VCC = 4V, VREF = 4V | 276 | ||
| Offset error (ADC) | -3.5 | 3.5 | LSB | VCC = 4V, VREF = 4V | 276 | ||
| ADC clock frequency | 50 | 200 | kHz | 276 |
CAD (KiCad official)
- Symbol:
ATMEGA48PA-MU - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
atmega48pa-mu-etched.step/atmega48pa-mu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega48pa-mu.step/atmega48pa-mu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (326 pp, sha256
626d81e6d4d566ae, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).