# ATMEGA328PB-MU

**Microchip Tech** · MICROCHIP · QFN-32-EP(5x5)

ATMEGA328PB-MU from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD[3] | bidirectional | Port D bit 3 is a bidirectional I/O pin with internal pull-up, multiplexed as INT1, OC2B, PCINT19, ADC/PTC function X3/Y11 per the I/O multiplexing table. |
| 2 | PD[4] | bidirectional | Port D bit 4 is a bidirectional I/O pin with internal pull-up, multiplexed as T0, XCK0, PCINT20 and PTC X4/Y12. |
| 3 | PE[0] | bidirectional | Port E bit 0 is a bidirectional I/O pin with internal pull-up, multiplexed as SDA1, ICP4, ACO, PCINT24 and PTC X8/Y16. |
| 4 | VCC | power_in | Digital supply voltage pin for the device, which must be operated within the 1.8 - 5.5V operating voltage range stated for the device. |
| 5 | GND | power_in | Ground reference pin for the digital circuitry. |
| 6 | PE[1] | bidirectional | Port E bit 1 is a bidirectional I/O pin with internal pull-up, multiplexed as SCL1, TC4, PCINT25 and PTC X9/Y17. |
| 7 | PB[6] | bidirectional | Port B bit 6 is a bidirectional I/O pin that, depending on the clock selection fuse settings, serves as input to the inverting oscillator amplifier and internal clock circuit, or as TOSC1 for the asynchronous Timer/Counter2. |
| 8 | PB[7] | bidirectional | Port B bit 7 is a bidirectional I/O pin that, depending on the clock selection fuse settings, serves as output from the inverting oscillator amplifier, or as TOSC2 for the asynchronous Timer/Counter2. |
| 9 | PD[5] | bidirectional | Port D bit 5 is a bidirectional I/O pin with internal pull-up, multiplexed as OC0B, T1, PCINT21 and PTC X5/Y13. |
| 10 | PD[6] | bidirectional | Port D bit 6 is a bidirectional I/O pin with internal pull-up, multiplexed as OC0A, AIN0 analog comparator input, PCINT22 and PTC X6/Y14. |
| 11 | PD[7] | bidirectional | Port D bit 7 is a bidirectional I/O pin with internal pull-up, multiplexed as AIN1 analog comparator input, PCINT23 and PTC X7. |
| 12 | PB[0] | bidirectional | Port B bit 0 is a bidirectional I/O pin with internal pull-up, multiplexed as ICP1, CLKO, PCINT0 and PTC X10/Y18. |
| 13 | PB[1] | bidirectional | Port B bit 1 is a bidirectional I/O pin with internal pull-up, multiplexed as OC1A, PCINT1 and PTC X11/Y19. |
| 14 | PB[2] | bidirectional | Port B bit 2 is a bidirectional I/O pin with internal pull-up, multiplexed as OC1B, SS0, PCINT2 and PTC X12/Y20. |
| 15 | PB[3] | bidirectional | Port B bit 3 is a bidirectional I/O pin with internal pull-up, multiplexed as OC2A, TXD1, MOSI0, PCINT3 and PTC X13/Y21. |
| 16 | PB[4] | bidirectional | Port B bit 4 is a bidirectional I/O pin with internal pull-up, multiplexed as RXD1, MISO0, PCINT4 and PTC X14/Y22. |
| 17 | PB[5] | bidirectional | Port B bit 5 is a bidirectional I/O pin with internal pull-up, multiplexed as XCK1, SCK0, PCINT5 and PTC X15/Y23. |
| 18 | AVCC | power_in | Supply voltage pin for the A/D Converter, PC[3:0] and PE[3:2], which should be connected to VCC even if the ADC is unused and through a low-pass filter if the ADC is used. |
| 19 | PE[2] | bidirectional | Port E bit 2 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC6 analog input (TQFP/VQFN only), ICP3, SS1, PCINT26 and PTC Y6. |
| 20 | AREF | power_in | Analog reference pin for the A/D Converter. |
| 21 | GND | power_in | Ground reference pin for the digital circuitry. |
| 22 | PE[3] | bidirectional | Port E bit 3 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC7 analog input (TQFP/VQFN only), T3, MOSI1, PCINT27 and PTC Y7. |
| 23 | PC[0] | bidirectional | Port C bit 0 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC0 analog input, MISO1, PCINT8 and PTC Y0; it is powered from AVCC. |
| 24 | PC[1] | bidirectional | Port C bit 1 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC1 analog input, SCK1, PCINT9 and PTC Y1; it is powered from AVCC. |
| 25 | PC[2] | bidirectional | Port C bit 2 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC2 analog input, PCINT10 and PTC Y2; it is powered from AVCC. |
| 26 | PC[3] | bidirectional | Port C bit 3 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC3 analog input, PCINT11 and PTC Y3; it is powered from AVCC. |
| 27 | PC[4] | bidirectional | Port C bit 4 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC4 analog input, SDA0, PCINT12 and PTC Y4; it is powered from VCC. |
| 28 | PC[5] | bidirectional | Port C bit 5 is a bidirectional I/O pin with internal pull-up, multiplexed as ADC5 analog input, SCL0, PCINT13 and PTC Y5; it is powered from VCC. |
| 29 | PC[6]/RESET | bidirectional | PC6 is a digital I/O pin if the RSTDISBL fuse is programmed; if the RSTDISBL fuse is unprogrammed it is a Reset input, where a low level longer than the minimum pulse length generates a Reset, and shorter pulses are not guaranteed to generate one. |
| 30 | PD[0] | bidirectional | Port D bit 0 is a bidirectional I/O pin with internal pull-up, multiplexed as OC3A, RXD0, PCINT16, PTC X0 and PTC Y8. |
| 31 | PD[1] | bidirectional | Port D bit 1 is a bidirectional I/O pin with internal pull-up, multiplexed as OC4A, TXD0, PCINT17, PTC X1 and PTC Y9. |
| 32 | PD[2] | bidirectional | Port D bit 2 is a bidirectional I/O pin with internal pull-up, multiplexed as INT0, OC3B/OC4B, PCINT18, PTC X2 and PTC Y10. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage |  | 1.8 |  | 5.5 | V | Features list, all speed grades | 2 |
| Operating temperature range (MU, Industrial) |  | -40 |  | 85 | °C | ATmega328PB-MU, Industrial operational range per ordering table | 6 |
| Speed grade, 1.8 V to 5.5 V |  | 0 |  | 4 | MHz | Supply 1.8 - 5.5 V | 2 |
| Speed grade, 2.7 V to 5.5 V |  | 0 |  | 10 | MHz | Supply 2.7 - 5.5 V | 2 |
| Speed grade, 4.5 V to 5.5 V |  | 0 |  | 20 | MHz | Supply 4.5 - 5.5 V | 2 |

## CAD (KiCad official)

- Symbol: `ATMEGA328PB-MU`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `atmega328pb-mu-etched.step` / `atmega328pb-mu-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atmega328pb-mu.step` / `atmega328pb-mu.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/40001907A.pdf) (17 pp, sha256 `6df6f6640dfc31f3`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/atmega328pb-mu-datasheet.pdf)