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ATMEGA3208-MUR

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleratmega3208-murfactory-2.0.0extractor-text

Verified ATMEGA3208-MUR

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA3208-MUR · VQFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 547-page datasheet
  • ✓distributor: lcsc C2055401, digikey 150-ATMEGA3208-MURTR-ND, mouser 556-ATMEGA3208-MUR
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-g2346mhe/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.530)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega3208-mur.kicad_sym✓ atmega3208-mur.kicad_mod✓ atmega3208-mur.step
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Contents

README

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ATMEGA3208-MUR

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)

ATMEGA3208-MUR from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose I/O pin PA3 with alternate functions TWI0 SCL (master/slave), USART0 XDIR, TCA0 WO3, TCB1 WO and CCL LUT0-OUT, selected through PORTMUX where alternate positions apply.
2 PA4 bidirectional General-purpose I/O pin PA4 with alternate functions USART0 TxD (alternate position), SPI0 MOSI and TCA0 WO4.
3 PA5 bidirectional General-purpose I/O pin PA5 with alternate functions USART0 RxD (alternate position), SPI0 MISO and TCA0 WO5.
4 PA6 bidirectional General-purpose I/O pin PA6 with alternate functions USART0 XCK (alternate position), SPI0 SCK and CCL LUT0-OUT (alternate position); PA6 supports full asynchronous interrupt detection, so it can wake the device from all sleep modes.
5 PA7 bidirectional General-purpose I/O pin PA7 with alternate functions CLKOUT, AC0 OUT, USART0 XDIR (alternate position), SPI0 SS and EVSYS EVOUTA (alternate position).
6 PC0 bidirectional General-purpose I/O pin PC0 with alternate functions USART1 TxD, SPI0 MOSI (alternate position), TCA0 WO0 (alternate position), TCB2 WO and CCL LUT1-IN0.
7 PC1 bidirectional General-purpose I/O pin PC1 with alternate functions USART1 RxD, SPI0 MISO (alternate position), TCA0 WO1 (alternate position), TCB3 WO (alternate position) and CCL LUT1-IN1.
8 PC2 bidirectional General-purpose I/O pin PC2 with alternate functions TWI0 SDA (master/slave) (alternate position), USART1 XCK, SPI0 SCK (alternate position), TCA0 WO2 (alternate position), EVSYS EVOUTC and CCL LUT1-IN2; PC2 supports full asynchronous interrupt detection.
9 PC3 bidirectional General-purpose I/O pin PC3 with alternate functions TWI0 SCL (master/slave) (alternate position), USART1 XDIR, SPI0 SS (alternate position), TCA0 WO3 (alternate position) and CCL LUT1-OUT.
10 PD0 bidirectional General-purpose I/O pin PD0 with analog input AIN0, alternate function TCA0 WO0 (alternate position) and CCL LUT2-IN0.
11 PD1 bidirectional General-purpose I/O pin PD1 with analog input AIN1, AC0 positive input P3, alternate function TCA0 WO1 (alternate position) and CCL LUT2-IN1.
12 PD2 bidirectional General-purpose I/O pin PD2 with analog input AIN2, AC0 positive input P0, alternate function TCA0 WO2 (alternate position), EVSYS EVOUTD and CCL LUT2-IN2; PD2 supports full asynchronous interrupt detection.
13 PD3 bidirectional General-purpose I/O pin PD3 with analog input AIN3, AC0 negative input N0, alternate function TCA0 WO3 (alternate position) and CCL LUT2-OUT.
14 PD4 bidirectional General-purpose I/O pin PD4 with analog input AIN4, AC0 positive input P1 and alternate function TCA0 WO4 (alternate position).
15 PD5 bidirectional General-purpose I/O pin PD5 with analog input AIN5, AC0 negative input N1 and alternate function TCA0 WO5 (alternate position).
16 PD6 bidirectional General-purpose I/O pin PD6 with analog input AIN6, AC0 positive input P2 and CCL LUT2-OUT (alternate position); PD6 supports full asynchronous interrupt detection.
17 PD7 bidirectional General-purpose I/O pin PD7 with VREFA external voltage reference input, analog input AIN7, AC0 negative input N2 and EVSYS EVOUTD (alternate position).
18 AVDD power_in Supply pin for the AVDD power domain, which feeds the GPIO on the AVDD domain and the analog functions; the device supply range is 1.8-5.5V.
19 GND power_in Ground reference pin for the device.
20 PF0 bidirectional General-purpose I/O pin PF0 that doubles as the TOSC1 crystal oscillator pin, with alternate functions USART2 TxD, TCA0 WO0 (alternate position) and CCL LUT3-IN0.
21 PF1 bidirectional General-purpose I/O pin PF1 that doubles as the TOSC2 crystal oscillator pin, with alternate functions USART2 RxD, TCA0 WO1 (alternate position) and CCL LUT3-IN1.
22 PF2 bidirectional General-purpose I/O pin PF2 with TWI0 SDA (slave) (alternate position), analog input AIN12, USART2 XCK (alternate position), TCA0 WO2 (alternate position), EVSYS EVOUTF and CCL LUT3-IN2; PF2 is not a full-async pin on this package.
23 PF3 bidirectional General-purpose I/O pin PF3 with TWI0 SCL (slave) (alternate position), analog input AIN13, USART2 XDIR (alternate position), TCA0 WO3 (alternate position) and CCL LUT3-OUT.
24 PF4 bidirectional General-purpose I/O pin PF4 with analog input AIN14, USART2 TxD (alternate position), TCA0 WO4 (alternate position) and TCB0 WO (alternate position).
25 PF5 bidirectional General-purpose I/O pin PF5 with analog input AIN15, USART2 RxD (alternate position), TCA0 WO5 (alternate position) and TCB1 WO (alternate position).
26 PF6 bidirectional General-purpose I/O pin PF6 that doubles as the RESET pin when RSTPINCFG is set to RESET, with USART2 XCK (alternate position) and CCL LUT3-OUT (alternate position) as alternate functions.
27 UPDI bidirectional Unified Program and Debug Interface pin used for programming and debugging the device.
28 VDD power_in Main power supply pin for the device, operating from 1.8V to 5.5V per the ordering information.
29 GND power_in Ground reference pin for the device.
30 PA0 bidirectional General-purpose I/O pin PA0 that doubles as the EXTCLK external clock input, with alternate functions USART0 TxD, TCA0 WO0 and CCL LUT0-IN0.
31 PA1 bidirectional General-purpose I/O pin PA1 with alternate functions USART0 RxD, TCA0 WO1 and CCL LUT0-IN1.
32 PA2 bidirectional General-purpose I/O pin PA2 with alternate functions TWI0 SDA (master/slave), USART0 XCK, TCA0 WO2, TCB0 WO, EVSYS EVOUTA and CCL LUT0-IN2; PA2 supports full asynchronous interrupt detection.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-32-EP(5x5)
Category Single Chip Microcomputer/Microcontroller
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 1.8 5.5 V 518
Operating temperature range (-MUR, -40°C to +85°C grade) -40 85 °C 518
Max. CPU speed 20 MHz 518

CAD (KiCad official)

  • Symbol: ATMEGA3208-MUR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: atmega3208-mur-etched.step / atmega3208-mur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega3208-mur.step / atmega3208-mur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (547 pp, sha256 8964762f5bd2fdc0, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF