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ATMEGA32-16AU
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownATMEGA32-16AU
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)
ATMEGA32-16AU from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB5 | bidirectional | Port B bit 5 is a bidirectional I/O pin with internal pull-up, and serves as SPI MOSI (master data output / slave data input) when SPI is enabled. |
| 2 | PB6 | bidirectional | Port B bit 6 is a bidirectional I/O pin with internal pull-up, and serves as SPI MISO (master data input / slave data output) when SPI is enabled. |
| 3 | PB7 | bidirectional | Port B bit 7 is a bidirectional I/O pin with internal pull-up, and serves as SPI clock (master clock output / slave clock input) when SPI is enabled. |
| 4 | RESET | input | Active-low reset input; a low level longer than the minimum pulse length (Table 15, p.37) generates a reset even if the clock is not running. |
| 5 | VCC | power_in | Digital supply voltage, 4.5 - 5.5V for ATmega32 (2.7 - 5.5V for ATmega32L). |
| 6 | GND | power_in | Ground. |
| 7 | XTAL2 | output | Output from the inverting oscillator amplifier. |
| 8 | XTAL1 | input | Input to the inverting oscillator amplifier and to the internal clock operating circuit. |
| 9 | PD0 | bidirectional | Port D bit 0 is a bidirectional I/O pin with internal pull-up, and serves as USART receive data input (RXD) when the receiver is enabled. |
| 10 | PD1 | bidirectional | Port D bit 1 is a bidirectional I/O pin with internal pull-up, and serves as USART transmit data output (TXD) when the transmitter is enabled. |
| 11 | PD2 | bidirectional | Port D bit 2 is a bidirectional I/O pin with internal pull-up, and serves as external interrupt source 0 (INT0). |
| 12 | PD3 | bidirectional | Port D bit 3 is a bidirectional I/O pin with internal pull-up, and serves as external interrupt source 1 (INT1). |
| 13 | PD4 | bidirectional | Port D bit 4 is a bidirectional I/O pin with internal pull-up, and serves as Timer/Counter1 output compare B match output (OC1B). |
| 14 | PD5 | bidirectional | Port D bit 5 is a bidirectional I/O pin with internal pull-up, and serves as Timer/Counter1 output compare A match output (OC1A). |
| 15 | PD6 | bidirectional | Port D bit 6 is a bidirectional I/O pin with internal pull-up, and serves as Timer/Counter1 input capture pin (ICP1). |
| 16 | PD7 (OC2) | bidirectional | Port D bit 7 is a bidirectional I/O pin with internal pull-up, and serves as Timer/Counter2 output compare match output (OC2). |
| 17 | VCC | power_in | Digital supply voltage, 4.5 - 5.5V for ATmega32 (2.7 - 5.5V for ATmega32L). |
| 18 | GND | power_in | Ground. |
| 19 | PC0 (SCL) | bidirectional | Port C bit 0 is a bidirectional I/O pin with internal pull-up, and serves as Two-wire Serial Interface clock line (SCL) when TWEN is set. |
| 20 | PC1 (SDA) | bidirectional | Port C bit 1 is a bidirectional I/O pin with internal pull-up, and serves as Two-wire Serial Interface data line (SDA) when TWEN is set. |
| 21 | PC2 (TCK) | bidirectional | Port C bit 2 is a bidirectional I/O pin with internal pull-up, and serves as JTAG test clock (TCK) when the JTAG interface is enabled, in which case it cannot be used as I/O. |
| 22 | PC3 (TMS) | bidirectional | Port C bit 3 is a bidirectional I/O pin with internal pull-up, and serves as JTAG test mode select (TMS) when the JTAG interface is enabled, in which case it cannot be used as I/O. |
| 23 | PC4 (TDO) | tri_state | Port C bit 4 serves as JTAG test data output (TDO) when the JTAG interface is enabled; the TDO pin is tri-stated unless TAP states that shift out data are entered. |
| 24 | PC5 (TDI) | bidirectional | Port C bit 5 is a bidirectional I/O pin with internal pull-up, and serves as JTAG test data input (TDI) when the JTAG interface is enabled, with the pull-up active even during reset. |
| 25 | PC6 (TOSC1) | bidirectional | Port C bit 6 is a bidirectional I/O pin, and serves as input to the inverting Timer Oscillator amplifier (TOSC1) when asynchronous Timer/Counter2 clocking is enabled. |
| 26 | PC7 (TOSC2) | bidirectional | Port C bit 7 is a bidirectional I/O pin, and serves as inverting output of the Timer Oscillator amplifier (TOSC2) when asynchronous Timer/Counter2 clocking is enabled. |
| 27 | AVCC | power_in | Supply voltage pin for Port A and the A/D Converter; it should be connected to VCC even if the ADC is not used, and through a low-pass filter if the ADC is used. |
| 28 | GND | power_in | Ground. |
| 29 | AREF | input | Analog reference pin for the A/D Converter. |
| 30 | PA7 (ADC7) | bidirectional | Port A bit 7 serves as ADC analog input channel 7, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 31 | PA6 (ADC6) | bidirectional | Port A bit 6 serves as ADC analog input channel 6, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 32 | PA5 (ADC5) | bidirectional | Port A bit 5 serves as ADC analog input channel 5, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 33 | PA4 (ADC4) | bidirectional | Port A bit 4 serves as ADC analog input channel 4, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 34 | PA3 (ADC3) | bidirectional | Port A bit 3 serves as ADC analog input channel 3, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 35 | PA2 (ADC2) | bidirectional | Port A bit 2 serves as ADC analog input channel 2, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 36 | PA1 (ADC1) | bidirectional | Port A bit 1 serves as ADC analog input channel 1, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 37 | PA0 (ADC0) | bidirectional | Port A bit 0 serves as ADC analog input channel 0, or as a bidirectional I/O pin with internal pull-up when the ADC is not used; pins are tri-stated on reset. |
| 38 | VCC | power_in | Digital supply voltage, 4.5 - 5.5V for ATmega32 (2.7 - 5.5V for ATmega32L). |
| 39 | GND | power_in | Ground. |
| 40 | PB0 (XCK/T0) | bidirectional | Port B bit 0 is a bidirectional I/O pin with internal pull-up, and serves as Timer/Counter0 external counter input (T0) and USART external clock (XCK). |
| 41 | PB1 (T1) | bidirectional | Port B bit 1 is a bidirectional I/O pin with internal pull-up, and serves as Timer/Counter1 external counter input (T1). |
| 42 | PB2 (AIN0/INT2) | bidirectional | Port B bit 2 is a bidirectional I/O pin with internal pull-up, and serves as Analog Comparator positive input (AIN0) and external interrupt source 2 (INT2); pull-up should be switched off when used as AIN0. |
| 43 | PB3 (AIN1/OC0) | bidirectional | Port B bit 3 is a bidirectional I/O pin with internal pull-up, and serves as Analog Comparator negative input (AIN1) and Timer/Counter0 output compare match output (OC0); pull-up should be switched off when used as AIN1. |
| 44 | PB4 (SS) | bidirectional | Port B bit 4 is a bidirectional I/O pin with internal pull-up, and serves as SPI slave select input (SS); when SPI is a slave, the pin is always an input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reset Pull-up Resistor | RRST | 30 | 60 | kΩ | 287 | ||
| I/O Pin Pull-up Resistor | Rpu | 20 | 50 | kΩ | 287 | ||
| Input Leakage Current I/O Pin (absolute value) | IIL | 1 | µA | VCC = 5.5V, pin low | 287 | ||
| Output Low Voltage (Ports A,B,C,D) | VOL | 0.7 | V | IOL = 20 mA, VCC = 5V | 287 | ||
| Output High Voltage (Ports A,B,C,D) | VOH | 4.2 | V | IOH = -20 mA, VCC = 5V | 287 | ||
| Input Low Voltage (except XTAL1 and RESET pins) | VIL | -0.5 | V | VCC = 4.5 - 5.5 | 287 | ||
| Input Low Voltage XTAL1 pin | VIL1 | -0.5 | V | VCC = 2.7 - 5.5 | 287 | ||
| Input Low Voltage RESET pin | VIL2 | -0.5 | V | VCC = 2.7 - 5.5 | 287 | ||
| Analog Comparator Input Leakage Current | IACLK | -50 | 50 | nA | VCC = 5V, Vin = VCC/2 | 288 | |
| Analog Comparator Input Offset Voltage | VACIO | 40 | mV | VCC = 5V, Vin = VCC/2 | 288 | ||
| Power Supply Current Active | ICC | 12 | 15 | mA | Active 8 MHz, VCC = 5V (ATmega32) | 288 | |
| Power Supply Current Idle | ICC | 5.5 | 8 | mA | Idle 8 MHz, VCC = 5V (ATmega32) | 288 | |
| Absolute Maximum Operating Temperature | TA | -55 | 125 | °C | 287 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 287 | ||
| Voltage on any pin except RESET with respect to Ground | -0.5 | V | with respect to ground; upper limit printed as VCC+0.5V | 287 | |||
| Voltage on RESET with respect to Ground | -0.5 | 13 | V | with respect to ground | 287 | ||
| Maximum Operating Voltage | 6 | V | 287 | ||||
| DC Current per I/O Pin | 40 | mA | 287 | ||||
| DC Current VCC and GND Pins | 400 | mA | TQFP/MLF package (PDIP: 200.0 mA) | 287 | |||
| Supply Voltage (ATmega32, 5 V variant) | VCC | 4.5 | 5.5 | V | ATmega32 (not ATmega32L); speed grade 16 MHz | 1 | |
| Oscillator Frequency | 1/tCLCL | 0 | 16 | MHz | VCC = 4.5V to 5.5V | 289 | |
| Operating Temperature (Industrial) | TA | -40 | 85 | °C | Industrial grade (AU suffix) | 287 | |
| Power-on Reset Threshold Voltage (rising) | VPOT | 1.4 | 2.3 | V | 37 | ||
| Power-on Reset Threshold Voltage (falling) | VPOT | 1.3 | 2.3 | V | 37 | ||
| Minimum pulse width on RESET Pin | tRST | 1.5 | µs | 37 | |||
| Brown-out Reset Threshold Voltage | VBOT | 3.6 | 4 | 4.2 | V | BODLEVEL = 0 | 37 |
| Minimum low voltage period for Brown-out Detection | tBOD | 2 | µs | BODLEVEL = 0 | 37 | ||
| Bandgap reference voltage | VBG | 1.15 | 1.23 | 1.35 | V | 41 | |
| Bandgap reference start-up time | tBG | 40 | 70 | µs | 41 | ||
| Bandgap reference current consumption | IBG | 10 | µA | 41 | |||
| Clock Period | tCLCL | 62.5 | ns | VCC = 4.5V to 5.5V | 289 | ||
| High Time | tCHCX | 25 | ns | VCC = 4.5V to 5.5V | 289 | ||
| Low Time | tCLCX | 25 | ns | VCC = 4.5V to 5.5V | 289 | ||
| Rise Time | tCLCH | 0.5 | µs | VCC = 4.5V to 5.5V | 289 | ||
| Fall Time | tCHCL | 0.5 | µs | VCC = 4.5V to 5.5V | 289 | ||
| Change in period from one clock cycle to the next | ΔtCLCL | 2 | % | VCC = 4.5V to 5.5V | 289 | ||
| Absolute Accuracy Single Ended Conversion (ADC clock 200 kHz) | 1.5 | LSB | Single ended conversion, VREF = 4V, VCC = 4V, ADC clock = 200 kHz | 293 | |||
| Absolute Accuracy Single Ended Conversion (ADC clock 1 MHz) | 3 | LSB | Single ended conversion, VREF = 4V, VCC = 4V, ADC clock = 1 MHz | 293 | |||
| Integral Non-Linearity (INL) | 0.75 | LSB | Single ended conversion, VREF = 4V, VCC = 4V, ADC clock = 200 kHz | 293 | |||
| Differential Non-linearity (DNL) | 0.25 | LSB | Single ended conversion, VREF = 4V, VCC = 4V, ADC clock = 200 kHz | 293 | |||
| Gain Error | 0.75 | LSB | Single ended conversion, VREF = 4V, VCC = 4V, ADC clock = 200 kHz | 293 | |||
| Offset Error | 0.75 | LSB | Single ended conversion, VREF = 4V, VCC = 4V, ADC clock = 200 kHz | 293 | |||
| ADC Clock Frequency | 50 | 1000 | kHz | 293 | |||
| ADC Conversion Time | 13 | 260 | µs | 293 | |||
| VREF Reference Voltage | VREF | 2 | V | 293 | |||
| ADC Conversion Output | 0 | 1023 | LSB | 293 | |||
| Internal Voltage Reference | VINT | 2.3 | 2.56 | 2.7 | V | 293 | |
| SCL Clock Frequency | fSCL | 0 | 400 | kHz | fCK > max(16fSCL, 250kHz) | 290 | |
| Output Low-voltage (TWI) | VOL | 0.4 | V | 3 mA sink current | 290 | ||
| Input Current each I/O Pin (TWI) | Ii | -10 | 10 | µA | 0.1VCC < Vi < 0.9VCC | 290 | |
| Capacitance for each I/O Pin | Ci | 10 | pF | 290 | |||
| Spikes Suppressed by Input Filter | tSP | 0 | 50 | ns | 290 | ||
| Low Period of the SCL Clock | tLOW | 4.7 | µs | fSCL ≤ 100 kHz | 290 | ||
| Low Period of the SCL Clock | tLOW | 1.3 | µs | fSCL > 100 kHz | 290 | ||
| Data Setup Time | tSU;DAT | 250 | ns | fSCL ≤ 100 kHz | 290 | ||
| Data Setup Time | tSU;DAT | 100 | ns | fSCL > 100 kHz | 290 | ||
| Bus Free Time between STOP and START | tBUF | 4.7 | µs | fSCL ≤ 100 kHz | 290 | ||
| Bus Free Time between STOP and START | tBUF | 1.3 | µs | fSCL > 100 kHz | 290 |
CAD (KiCad official)
- Symbol:
ATMEGA32-16AU - Footprint:
Package_QFP:TQFP-44_10x10mm_P0.8mm - 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
atmega32-16au-etched.step/atmega32-16au-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega32-16au.step/atmega32-16au.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (347 pp, sha256
96f068da63286072, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).