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ATMEGA16U2-MUR

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Microchip Tech Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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ATMEGA16U2-MUR

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)

ATMEGA16U2-MUR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XTAL1 input Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
2 XTAL2/PC0 bidirectional Output from the inverting oscillator amplifier if enabled by fuse; also serves as generic I/O PC0.
3 GND power_in Ground.
4 VCC power_in Digital supply voltage.
5 PC2 bidirectional Port C bit 2 I/O with internal pull-up; alternate functions PCINT11 and AIN2.
6 PD0 bidirectional Port D bit 0 I/O with internal pull-up; alternate functions INT0 and OC0B.
7 PD1 bidirectional Port D bit 1 I/O with internal pull-up; alternate functions INT1 and AIN0 (analog comparator positive input).
8 PD2 bidirectional Port D bit 2 I/O with internal pull-up; alternate functions INT2, AIN1 (analog comparator negative input) and RXD1.
9 PD3 bidirectional Port D bit 3 I/O with internal pull-up; alternate functions INT3 and TXD1.
10 PD4 bidirectional Port D bit 4 I/O with internal pull-up; alternate function INT5 (AIN3 per pinout).
11 PD5 bidirectional Port D bit 5 I/O with internal pull-up; alternate functions XCK1 (USART1 external clock), AIN4 and PCINT12.
12 PD6 bidirectional Port D bit 6 I/O with internal pull-up; alternate functions INT6, AIN5 and RTS (USART1 receiver flow control).
13 PD7 bidirectional Port D bit 7 I/O with internal pull-up; alternate functions HWB (hardware boot), T0, INT7, AIN6 and CTS.
14 PB0 bidirectional Port B bit 0 I/O with internal pull-up; SPI slave select SS and PCINT0.
15 PB1 bidirectional Port B bit 1 I/O with internal pull-up; SPI clock SCLK and PCINT1.
16 PB2 bidirectional Port B bit 2 I/O with internal pull-up; MOSI/PDI and PCINT2.
17 PB3 bidirectional Port B bit 3 I/O with internal pull-up; MISO/PDO and PCINT3.
18 PB4 bidirectional Port B bit 4 I/O with internal pull-up; T1 and PCINT4.
19 PB5 bidirectional Port B bit 5 I/O with internal pull-up; PCINT5.
20 PB6 bidirectional Port B bit 6 I/O with internal pull-up; PCINT6.
21 PB7 bidirectional Port B bit 7 I/O with internal pull-up; OC0A, OC1C and PCINT7.
22 PC7 bidirectional Port C bit 7 I/O with internal pull-up; ICP1, INT4 and CLKO clock output.
23 PC6 bidirectional Port C bit 6 I/O with internal pull-up; PCINT8 and OC1A.
24 RESET/PC1/dW bidirectional Active-low reset input (low longer than minimum pulse length generates a reset); alternatively debugWire channel or generic I/O depending on RSTDISBL and DWEN fuses.
25 PC5 bidirectional Port C bit 5 I/O with internal pull-up; PCINT9 and OC1B.
26 PC4 bidirectional Port C bit 4 I/O with internal pull-up; PCINT10.
27 UCAP passive USB pads internal regulator output supply voltage; connect an external 1 µF capacitor.
28 UGND power_in USB ground.
29 D+ bidirectional USB full speed positive data upstream port.
30 D- bidirectional USB full speed negative data upstream port.
31 UVCC power_in USB pads internal regulator input supply voltage.
32 AVCC power_in Supply voltage for analog features (analog comparator, PLL); should be externally connected to VCC through a low-pass filter.
33 EP power_in Large center pad underneath the QFN package; should be soldered to ground on the board for mechanical stability.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature -55 125 °C 264
Storage Temperature -65 150 °C 264
Maximum Operating Voltage 6 V 264
Voltage on RESET with respect to Ground -0.5 13 V 264
Voltage on UVcc with respect to Ground UVcc -0.5 6 V 264
DC Current per I/O Pin 40 mA 264
DC Current VCC and GND Pins 200 mA 264
Supply Voltage VCC 2.7 5.5 V Operating voltage range 264
Operating Temperature (industrial) TA -40 85 °C Industrial range 264
Maximum Frequency 8 MHz VCC = 2.7V, industrial range 1
Maximum Frequency 16 MHz VCC = 4.5V, industrial range 1
Input Low Voltage, Standard IOs VIL -0.5 0.8 V VCC = 2.7V - 5.5V 264
Input High Voltage, Standard IOs VIH 2 V VCC = 2.7V - 5.5V 264
Output Low Voltage, Standard IOs, MOSI/MISO pins VOL 0.7 V IOL = 10mA, VCC = 5V 264
Output Low Voltage, Standard IOs, MOSI/MISO pins VOL 0.5 V IOL = 5mA, VCC = 3V 264
Output High Voltage, Standard IOs, MOSI/MISO pins VOH 4.2 V IOH = -10mA, VCC = 5V 264
Output High Voltage, Standard IOs, MOSI/MISO pins VOH 2.3 V IOH = -5mA, VCC = 3V 264
Input Leakage Current I/O Pin IIL 1 μA VCC = 5.5V, pin low (absolute value) 264
Reset Pull-up Resistor RRST 30 60 k 264
I/O Pin Pull-up Resistor RPU 20 50 k 264
USB D+ Internal Pull-Up RPUDP 900 1500 Idle mode 265
USB D+ Internal Pull-Up RPUDP 1425 3090 Streaming mode 265
USB Series resistor (external) Rusb -5 5 % External; nominal 22 (unit not printed) 265
Regulator Output Voltage Vreg 3 3.3 3.6 V Vcc4.0V, I100mA, CUCAP=1μF±20% 265
UVcc (USB pads regulator input supply) UVcc 4 5.5 V 265
Analog Comparator Input Offset Voltage VACIO 40 mV VCC = 5V, Vin = VCC/2 265
Analog Comparator Input Leakage Current IACLK -50 50 nA VCC = 5V, Vin = VCC/2 265
Analog Comparator Propagation Delay tACID 750 ns VCC = 2.7V 265
Analog Comparator Propagation Delay tACID 500 ns VCC = 4.0V 265
Power Supply Current, Active ICC 4 6 mA Active 8 MHz, VCC = 3V, regulator disabled 265
Power Supply Current, Active ICC 13.5 21 mA Active 16 MHz, VCC = 5V, regulator enabled 265
Power Supply Current, Idle ICC 0.8 1.2 mA Idle 8 MHz, VCC = 3V, regulator disabled 265
Power Supply Current, Idle ICC 3.2 4 mA Idle 16 MHz, VCC = 5V, regulator enabled 265
Power Supply Current, Power-down ICC 5 10 μA WDT disabled, regulator disabled, VCC = 3V 265
Power Supply Current, Power-down ICC 10 15 μA WDT enabled, regulator disabled, VCC = 3V 265
Power Supply Current, Power-down ICC 40 65 μA WDT, BOD, regulator enabled, Vcc = 5V 265
Power-on Reset Threshold Voltage (rising) VPOT 1.4 2.3 V 267
Power-on Reset Threshold Voltage (falling) VPOT 1.3 2.3 V 267
VCC Start Voltage to ensure internal Power-on Reset signal VPOR -0.1 0.1 V 267
VCC Rise Rate to ensure internal Power-on Reset signal VCCRR 0.3 V/ms 267
Minimum pulse width on RESET Pin tRST 400 ns 5V, 25°C 267
Bandgap reference voltage VBG 1 1.1 1.2 V VCC = 2.7V - 5.5V 267
Brown-out Detector trigger level VBOT 2.5 2.7 2.9 V BODLEVEL 2..0 = 110 268
Brown-out Detector trigger level VBOT 4.1 4.3 4.5 V BODLEVEL 2..0 = 000 268
Bandgap reference start-up time tBG 40 70 μs 267
Minimum pulse width for asynchronous external interrupt tINT 50 ns 268
Oscillator Frequency 1/tCLCL 0 8 MHz VCC = 2.7-5.5V 267
Oscillator Frequency 1/tCLCL 0 16 MHz VCC = 4.5-5.5V 267
Clock Period tCLCL 125 ns VCC = 2.7-5.5V 267
Clock Period tCLCL 62.5 ns VCC = 4.5-5.5V 267
High Time tCHCX 50 ns VCC = 2.7-5.5V 267
High Time tCHCX 25 ns VCC = 4.5-5.5V 267
Low Time tCLCX 50 ns VCC = 2.7-5.5V 267
Low Time tCLCX 25 ns VCC = 4.5-5.5V 267
Calibration Accuracy of Internal RC Oscillator (factory) -10 10 % 8.0 MHz, 3V, 25C, factory calibration 266
Calibration Accuracy of Internal RC Oscillator (user) -1 1 % 7.3 - 8.1 MHz, 2.7V - 5.5V, -40C - 85C 266
Standby mode 8MHz XTAL, WDT disabled, BOD enabled, regulator disabled ICC 250 μA Vcc = 3V 265
Standby mode 8MHz XTAL, WDT disabled, BOD, regulator enabled ICC 350 μA Vcc = 5V 265
Brown-out Detector Hysteresis VHYST 50 mV 267

CAD (KiCad official)

  • Symbol: ATMEGA16U2-MUR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: atmega16u2-mur-etched.step / atmega16u2-mur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega16u2-mur.step / atmega16u2-mur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (310 pp, sha256 182d44b383463202, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF