component
ATMEGA169PA-AUR
Public Made by Adomby adom
Microchip Tech MICROCHIP, TQFP-64(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ATMEGA169PA-AUR
Microchip Tech · MICROCHIP · TQFP-64(14x14)
ATMEGA169PA-AUR from Microchip Tech, in a TQFP-64(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LCDCAP | passive | LCD power reservoir pin needing an external capacitor (typical > 470 nF) if the LCD module is enabled and uses internal power. |
| 2 | PE0 (RXD/PCINT0) | bidirectional | Port E bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions RXD and PCINT0. |
| 3 | PE1 (TXD/PCINT1) | bidirectional | Port E bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions TXD and PCINT1. |
| 4 | PE2 (XCK/AIN0/PCINT2) | bidirectional | Port E bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions XCK, AIN0 and PCINT2. |
| 5 | PE3 (AIN1/PCINT3) | bidirectional | Port E bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions AIN1 and PCINT3. |
| 6 | PE4 (USCK/SCL/PCINT4) | bidirectional | Port E bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions USCK, SCL and PCINT4. |
| 7 | PE5 (DI/SDA/PCINT5) | bidirectional | Port E bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions DI, SDA and PCINT5. |
| 8 | PE6 (DO/PCINT6) | bidirectional | Port E bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions DO and PCINT6. |
| 9 | PE7 (CLKO/PCINT7) | bidirectional | Port E bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions CLKO and PCINT7. |
| 10 | PB0 (SS/PCINT8) | bidirectional | Port B bit 0, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions SS and PCINT8. |
| 11 | PB1 (SCK/PCINT9) | bidirectional | Port B bit 1, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions SCK and PCINT9. |
| 12 | PB2 (MOSI/PCINT10) | bidirectional | Port B bit 2, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions MOSI and PCINT10. |
| 13 | PB3 (MISO/PCINT11) | bidirectional | Port B bit 3, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions MISO and PCINT11. |
| 14 | PB4 (OC0A/PCINT12) | bidirectional | Port B bit 4, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC0A and PCINT12. |
| 15 | PB5 (OC1A/PCINT13) | bidirectional | Port B bit 5, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC1A and PCINT13. |
| 16 | PB6 (OC1B/PCINT14) | bidirectional | Port B bit 6, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC1B and PCINT14. |
| 17 | PB7 (OC2A/PCINT15) | bidirectional | Port B bit 7, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC2A and PCINT15. |
| 18 | PG3 (T1/SEG24) | bidirectional | Port G bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions T1 and LCD segment SEG24. |
| 19 | PG4 (T0/SEG23) | bidirectional | Port G bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions T0 and LCD segment SEG23. |
| 20 | RESET/PG5 | input | Reset input; a low level longer than the minimum pulse length generates a reset even if the clock is not running, and the pin is also Port G bit 5. |
| 21 | VCC | power_in | Digital supply voltage. |
| 22 | GND | power_in | Ground. |
| 23 | XTAL2 (TOSC2) | output | Output from the inverting oscillator amplifier; also TOSC2 for the asynchronous timer oscillator. |
| 24 | XTAL1 (TOSC1) | input | Input to the inverting oscillator amplifier and input to the internal clock operating circuit; also TOSC1 for the asynchronous timer oscillator. |
| 25 | PD0 (ICP1/SEG22) | bidirectional | Port D bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions ICP1 and LCD segment SEG22. |
| 26 | PD1 (INT0/SEG21) | bidirectional | Port D bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions INT0 and LCD segment SEG21. |
| 27 | PD2 (SEG20) | bidirectional | Port D bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG20. |
| 28 | PD3 (SEG19) | bidirectional | Port D bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG19. |
| 29 | PD4 (SEG18) | bidirectional | Port D bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG18. |
| 30 | PD5 (SEG17) | bidirectional | Port D bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG17. |
| 31 | PD6 (SEG16) | bidirectional | Port D bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG16. |
| 32 | PD7 (SEG15) | bidirectional | Port D bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG15. |
| 33 | PG0 (SEG14) | bidirectional | Port G bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG14. |
| 34 | PG1 (SEG13) | bidirectional | Port G bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG13. |
| 35 | PC0 (SEG12) | bidirectional | Port C bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG12. |
| 36 | PC1 (SEG11) | bidirectional | Port C bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG11. |
| 37 | PC2 (SEG10) | bidirectional | Port C bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG10. |
| 38 | PC3 (SEG9) | bidirectional | Port C bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG9. |
| 39 | PC4 (SEG8) | bidirectional | Port C bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG8. |
| 40 | PC5 (SEG7) | bidirectional | Port C bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG7. |
| 41 | PC6 (SEG6) | bidirectional | Port C bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG6. |
| 42 | PC7 (SEG5) | bidirectional | Port C bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG5. |
| 43 | PG2 (SEG4) | bidirectional | Port G bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG4. |
| 44 | PA7 (SEG3) | bidirectional | Port A bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG3. |
| 45 | PA6 (SEG2) | bidirectional | Port A bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG2. |
| 46 | PA5 (SEG1) | bidirectional | Port A bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG1. |
| 47 | PA4 (SEG0) | bidirectional | Port A bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG0. |
| 48 | PA3 (COM3) | bidirectional | Port A bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM3. |
| 49 | PA2 (COM2) | bidirectional | Port A bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM2. |
| 50 | PA1 (COM1) | bidirectional | Port A bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM1. |
| 51 | PA0 (COM0) | bidirectional | Port A bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM0. |
| 52 | VCC | power_in | Digital supply voltage. |
| 53 | GND | power_in | Ground. |
| 54 | PF7 (ADC7/TDI) | bidirectional | Port F bit 7, ADC input channel 7 and JTAG TDI, with selectable pull-up that is activated even during reset if JTAG is enabled. |
| 55 | PF6 (ADC6/TDO) | bidirectional | Port F bit 6, ADC input channel 6 and JTAG TDO, with selectable internal pull-up, tri-stated during reset. |
| 56 | PF5 (ADC5/TMS) | bidirectional | Port F bit 5, ADC input channel 5 and JTAG TMS, with selectable pull-up that is activated even during reset if JTAG is enabled. |
| 57 | PF4 (ADC4/TCK) | bidirectional | Port F bit 4, ADC input channel 4 and JTAG TCK, with selectable pull-up that is activated even during reset if JTAG is enabled. |
| 58 | PF3 (ADC3) | bidirectional | Port F bit 3, ADC input channel 3 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 59 | PF2 (ADC2) | bidirectional | Port F bit 2, ADC input channel 2 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 60 | PF1 (ADC1) | bidirectional | Port F bit 1, ADC input channel 1 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 61 | PF0 (ADC0) | bidirectional | Port F bit 0, ADC input channel 0 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 62 | AREF | input | Analog reference pin for the A/D Converter. |
| 63 | GND | power_in | Ground. |
| 64 | AVCC | power_in | Supply voltage pin for Port F and the A/D Converter, to be externally connected to VCC even if the ADC is not used, and through a low-pass filter if the ADC is used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
ATMEGA169PA-AUR - Footprint:
Package_QFP:TQFP-64_14x14mm_P0.8mm - 3D model: TQFP-64(14x14) (KiCad packages3D, STEP)
- 3D model files:
atmega169pa-aur-etched.step/atmega169pa-aur-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega169pa-aur.step/atmega169pa-aur.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (39 pp, sha256
d4323bf006acd3e2, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATMEGA169PA-AUR
**Microchip Tech** · MICROCHIP · TQFP-64(14x14)
ATMEGA169PA-AUR from Microchip Tech, in a TQFP-64(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LCDCAP | passive | LCD power reservoir pin needing an external capacitor (typical > 470 nF) if the LCD module is enabled and uses internal power. |
| 2 | PE0 (RXD/PCINT0) | bidirectional | Port E bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions RXD and PCINT0. |
| 3 | PE1 (TXD/PCINT1) | bidirectional | Port E bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions TXD and PCINT1. |
| 4 | PE2 (XCK/AIN0/PCINT2) | bidirectional | Port E bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions XCK, AIN0 and PCINT2. |
| 5 | PE3 (AIN1/PCINT3) | bidirectional | Port E bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions AIN1 and PCINT3. |
| 6 | PE4 (USCK/SCL/PCINT4) | bidirectional | Port E bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions USCK, SCL and PCINT4. |
| 7 | PE5 (DI/SDA/PCINT5) | bidirectional | Port E bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions DI, SDA and PCINT5. |
| 8 | PE6 (DO/PCINT6) | bidirectional | Port E bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions DO and PCINT6. |
| 9 | PE7 (CLKO/PCINT7) | bidirectional | Port E bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions CLKO and PCINT7. |
| 10 | PB0 (SS/PCINT8) | bidirectional | Port B bit 0, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions SS and PCINT8. |
| 11 | PB1 (SCK/PCINT9) | bidirectional | Port B bit 1, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions SCK and PCINT9. |
| 12 | PB2 (MOSI/PCINT10) | bidirectional | Port B bit 2, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions MOSI and PCINT10. |
| 13 | PB3 (MISO/PCINT11) | bidirectional | Port B bit 3, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions MISO and PCINT11. |
| 14 | PB4 (OC0A/PCINT12) | bidirectional | Port B bit 4, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC0A and PCINT12. |
| 15 | PB5 (OC1A/PCINT13) | bidirectional | Port B bit 5, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC1A and PCINT13. |
| 16 | PB6 (OC1B/PCINT14) | bidirectional | Port B bit 6, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC1B and PCINT14. |
| 17 | PB7 (OC2A/PCINT15) | bidirectional | Port B bit 7, bi-directional I/O with selectable internal pull-up and better drive capability than other ports, tri-stated during reset; alternate functions OC2A and PCINT15. |
| 18 | PG3 (T1/SEG24) | bidirectional | Port G bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions T1 and LCD segment SEG24. |
| 19 | PG4 (T0/SEG23) | bidirectional | Port G bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions T0 and LCD segment SEG23. |
| 20 | RESET/PG5 | input | Reset input; a low level longer than the minimum pulse length generates a reset even if the clock is not running, and the pin is also Port G bit 5. |
| 21 | VCC | power_in | Digital supply voltage. |
| 22 | GND | power_in | Ground. |
| 23 | XTAL2 (TOSC2) | output | Output from the inverting oscillator amplifier; also TOSC2 for the asynchronous timer oscillator. |
| 24 | XTAL1 (TOSC1) | input | Input to the inverting oscillator amplifier and input to the internal clock operating circuit; also TOSC1 for the asynchronous timer oscillator. |
| 25 | PD0 (ICP1/SEG22) | bidirectional | Port D bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions ICP1 and LCD segment SEG22. |
| 26 | PD1 (INT0/SEG21) | bidirectional | Port D bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate functions INT0 and LCD segment SEG21. |
| 27 | PD2 (SEG20) | bidirectional | Port D bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG20. |
| 28 | PD3 (SEG19) | bidirectional | Port D bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG19. |
| 29 | PD4 (SEG18) | bidirectional | Port D bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG18. |
| 30 | PD5 (SEG17) | bidirectional | Port D bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG17. |
| 31 | PD6 (SEG16) | bidirectional | Port D bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG16. |
| 32 | PD7 (SEG15) | bidirectional | Port D bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG15. |
| 33 | PG0 (SEG14) | bidirectional | Port G bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG14. |
| 34 | PG1 (SEG13) | bidirectional | Port G bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG13. |
| 35 | PC0 (SEG12) | bidirectional | Port C bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG12. |
| 36 | PC1 (SEG11) | bidirectional | Port C bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG11. |
| 37 | PC2 (SEG10) | bidirectional | Port C bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG10. |
| 38 | PC3 (SEG9) | bidirectional | Port C bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG9. |
| 39 | PC4 (SEG8) | bidirectional | Port C bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG8. |
| 40 | PC5 (SEG7) | bidirectional | Port C bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG7. |
| 41 | PC6 (SEG6) | bidirectional | Port C bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG6. |
| 42 | PC7 (SEG5) | bidirectional | Port C bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG5. |
| 43 | PG2 (SEG4) | bidirectional | Port G bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG4. |
| 44 | PA7 (SEG3) | bidirectional | Port A bit 7, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG3. |
| 45 | PA6 (SEG2) | bidirectional | Port A bit 6, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG2. |
| 46 | PA5 (SEG1) | bidirectional | Port A bit 5, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG1. |
| 47 | PA4 (SEG0) | bidirectional | Port A bit 4, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD segment SEG0. |
| 48 | PA3 (COM3) | bidirectional | Port A bit 3, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM3. |
| 49 | PA2 (COM2) | bidirectional | Port A bit 2, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM2. |
| 50 | PA1 (COM1) | bidirectional | Port A bit 1, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM1. |
| 51 | PA0 (COM0) | bidirectional | Port A bit 0, bi-directional I/O with selectable internal pull-up, tri-stated during reset; alternate function LCD common COM0. |
| 52 | VCC | power_in | Digital supply voltage. |
| 53 | GND | power_in | Ground. |
| 54 | PF7 (ADC7/TDI) | bidirectional | Port F bit 7, ADC input channel 7 and JTAG TDI, with selectable pull-up that is activated even during reset if JTAG is enabled. |
| 55 | PF6 (ADC6/TDO) | bidirectional | Port F bit 6, ADC input channel 6 and JTAG TDO, with selectable internal pull-up, tri-stated during reset. |
| 56 | PF5 (ADC5/TMS) | bidirectional | Port F bit 5, ADC input channel 5 and JTAG TMS, with selectable pull-up that is activated even during reset if JTAG is enabled. |
| 57 | PF4 (ADC4/TCK) | bidirectional | Port F bit 4, ADC input channel 4 and JTAG TCK, with selectable pull-up that is activated even during reset if JTAG is enabled. |
| 58 | PF3 (ADC3) | bidirectional | Port F bit 3, ADC input channel 3 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 59 | PF2 (ADC2) | bidirectional | Port F bit 2, ADC input channel 2 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 60 | PF1 (ADC1) | bidirectional | Port F bit 1, ADC input channel 1 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 61 | PF0 (ADC0) | bidirectional | Port F bit 0, ADC input channel 0 or general I/O with selectable internal pull-up, tri-stated during reset. |
| 62 | AREF | input | Analog reference pin for the A/D Converter. |
| 63 | GND | power_in | Ground. |
| 64 | AVCC | power_in | Supply voltage pin for Port F and the A/D Converter, to be externally connected to VCC even if the ADC is not used, and through a low-pass filter if the ADC is used. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## CAD (KiCad official)
- Symbol: `ATMEGA169PA-AUR`
- Footprint: `Package_QFP:TQFP-64_14x14mm_P0.8mm`
- 3D model: TQFP-64(14x14) (KiCad packages3D, STEP)
- 3D model files: `atmega169pa-aur-etched.step` / `atmega169pa-aur-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atmega169pa-aur.step` / `atmega169pa-aur.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8284-8-bit-AVR-microcontroller-ATmega169A_PA_329A_PA_3290A_PA_649A_P_6490A_P_summary.pdf) (39 pp, sha256 `d4323bf006acd3e2`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/atmega169pa-aur-datasheet.pdf)