component
ATMEGA168PA-MU
Public Made by Adomby adom
Microchip Tech MICROCHIP, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ATMEGA168PA-MU
Microchip Tech · MICROCHIP · VQFN-32-EP(5x5)
ATMEGA168PA-MU from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD3/INT1/OC2B/PCINT19 | bidirectional | Port D bit 3 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as external interrupt 1 input and OC2B output. |
| 2 | PD4/XCK/T0/PCINT20 | bidirectional | Port D bit 4 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as USART external clock XCK and Timer/Counter0 input T0. |
| 3 | GND | power_in | Ground reference for the digital supply. |
| 4 | VCC | power_in | Digital supply voltage; the operating range is 2.7V to 5.5V. |
| 5 | GND | power_in | Ground reference for the digital supply. |
| 6 | VCC | power_in | Digital supply voltage; the operating range is 2.7V to 5.5V. |
| 7 | PB6/XTAL1/TOSC1/PCINT6 | bidirectional | Port B bit 6 serves as the chip clock oscillator input XTAL1 or timer oscillator TOSC1 depending on the clock fuse settings, and cannot be used as I/O when used as a clock pin. |
| 8 | PB7/XTAL2/TOSC2/PCINT7 | bidirectional | Port B bit 7 serves as the inverting oscillator amplifier output XTAL2 or timer oscillator TOSC2 depending on the clock fuse settings, and cannot be used as I/O when used as a clock pin. |
| 9 | PD5/T1/OC0B/PCINT21 | bidirectional | Port D bit 5 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as Timer/Counter1 external counter input T1 and OC0B output. |
| 10 | PD6/AIN0/OC0A/PCINT22 | bidirectional | Port D bit 6 is a bidirectional I/O pin that serves as analog comparator positive input AIN0 (pull-up should be off in that use) and OC0A output. |
| 11 | PD7/AIN1/PCINT23 | bidirectional | Port D bit 7 is a bidirectional I/O pin that serves as analog comparator negative input AIN1 (pull-up should be off in that use). |
| 12 | PB0/ICP1/CLKO/PCINT0 | bidirectional | Port B bit 0 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as Timer/Counter1 input capture ICP1 and divided clock output CLKO. |
| 13 | PB1/OC1A/PCINT1 | bidirectional | Port B bit 1 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as Timer/Counter1 output compare A output OC1A. |
| 14 | PB2/SS/OC1B/PCINT2 | bidirectional | Port B bit 2 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI slave select SS and Timer/Counter1 output compare B output OC1B. |
| 15 | PB3/MOSI/OC2A/PCINT3 | bidirectional | Port B bit 3 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI MOSI and Timer/Counter2 output compare A output OC2A. |
| 16 | PB4/MISO/PCINT4 | bidirectional | Port B bit 4 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI master input/slave output MISO. |
| 17 | PB5/SCK/PCINT5 | bidirectional | Port B bit 5 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI clock SCK. |
| 18 | AVCC | power_in | Supply voltage pin for the A/D converter, PC3:0 and ADC7:6, which should be connected to VCC even if the ADC is not used. |
| 19 | ADC6 | input | Analog input channel 6 of the 10-bit A/D converter, powered from the analog supply (TQFP and QFN package only). |
| 20 | AREF | input | Analog reference pin for the A/D converter. |
| 21 | GND | power_in | Ground reference for the digital supply. |
| 22 | ADC7 | input | Analog input channel 7 of the 10-bit A/D converter, powered from the analog supply (TQFP and QFN package only). |
| 23 | PC0/ADC0/PCINT8 | bidirectional | Port C bit 0 is a 7-bit port pin that is tri-stated on reset, also serving as ADC input channel 0 using analog power. |
| 24 | PC1/ADC1/PCINT9 | bidirectional | Port C bit 1 is a port pin that is tri-stated on reset, also serving as ADC input channel 1 using analog power. |
| 25 | PC2/ADC2/PCINT10 | bidirectional | Port C bit 2 is a port pin that is tri-stated on reset, also serving as ADC input channel 2 using analog power. |
| 26 | PC3/ADC3/PCINT11 | bidirectional | Port C bit 3 is a port pin that is tri-stated on reset, also serving as ADC input channel 3 using analog power. |
| 27 | PC4/ADC4/SDA/PCINT12 | bidirectional | Port C bit 4 is a port pin that is tri-stated on reset, also serving as 2-wire serial data SDA and ADC input channel 4 using digital power. |
| 28 | PC5/ADC5/SCL/PCINT13 | bidirectional | Port C bit 5 is a port pin that is tri-stated on reset, also serving as 2-wire serial clock SCL and ADC input channel 5 using digital power. |
| 29 | PC6/RESET/PCINT14 | input | When the RSTDISBL fuse is unprogrammed this pin is an active-low reset input, and a low level longer than the minimum pulse length generates a reset; when programmed it acts as I/O with electrical characteristics differing from other port C pins. |
| 30 | PD0/RXD/PCINT16 | bidirectional | Port D bit 0 is a bidirectional I/O pin that serves as USART receive data input RXD when the USART receiver is enabled. |
| 31 | PD1/TXD/PCINT17 | bidirectional | Port D bit 1 is a bidirectional I/O pin that serves as USART transmit data output TXD and is configured as an output whenever the USART transmitter is enabled. |
| 32 | PD2/INT0/PCINT18 | bidirectional | Port D bit 2 is a bidirectional I/O pin that serves as external interrupt source 0 INT0. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature | -55 | 125 | °C | 268 | |||
| Storage temperature | -65 | 150 | °C | 268 | |||
| Voltage on any pin except RESET with respect to ground | -0.5 | V | 268 | ||||
| Voltage on RESET with respect to ground | -0.5 | 13 | V | 268 | |||
| Maximum operating voltage | 6 | V | 268 | ||||
| DC current per I/O pin | 40 | mA | 268 | ||||
| DC current VCC and GND pins | 200 | mA | 268 | ||||
| Supply voltage | VCC | 2.7 | 5.5 | V | TA = -40°C to 125°C | 269 | |
| Input leakage current I/O pin (low) | IIL | 1 | µA | VCC = 5.5V, pin low (absolute value) | 269 | ||
| Input leakage current I/O pin (high) | IIH | 1 | µA | VCC = 5.5V, pin high (absolute value) | 269 | ||
| Reset pull-up resistor | RRST | 30 | 60 | k | VCC = 5V, Vin = 0V | 269 | |
| I/O pin pull-up resistor | RPU | 20 | 50 | k | 269 | ||
| Analog comparator input offset voltage | VACIO | 40 | mV | VCC = 5V, 0.1VCC < Vin < VCC - 100mV | 269 | ||
| Analog comparator input leakage current | IACLK | -50 | 50 | nA | 0.1VCC < Vin < VCC, 100mV | 269 | |
| Output low voltage except RESET pin (20mA) | VOL | 0.8 | V | IOL = 20mA, VCC = 5V | 269 | ||
| Output low voltage except RESET pin (5mA) | VOL | 0.5 | V | IOL = 5mA, VCC = 3V | 269 | ||
| Output high voltage except reset pin (20mA) | VOH | 4.1 | V | IOH = -20mA, VCC = 5V | 269 | ||
| Output high voltage except reset pin (10mA) | VOH | 2.3 | V | IOH = -10mA, VCC = 3V | 269 | ||
| Active supply current 4MHz | ICC | 1.3 | 2.4 | mA | Active 4MHz, VCC = 3V | 270 | |
| Active supply current 8MHz | ICC | 4.6 | 10 | mA | Active 8MHz, VCC = 5V | 270 | |
| Active supply current 16MHz | ICC | 8.4 | 16 | mA | Active 16MHz, VCC = 5V | 270 | |
| Idle supply current 4MHz | ICC | 0.2 | 0.6 | mA | Idle 4MHz, VCC = 3V | 270 | |
| Idle supply current 8MHz | ICC | 0.9 | 1.6 | mA | Idle 8MHz, VCC = 5V | 270 | |
| Idle supply current 16MHz | ICC | 1.8 | 4 | mA | Idle 16MHz, VCC = 5V | 270 | |
| Power-down current WDT enabled 3V | ICC | 4.2 | 44 | µA | Power-down mode, WDT enabled, VCC = 3V | 270 | |
| Power-down current WDT enabled 5V | ICC | 6.2 | 66 | µA | Power-down mode, WDT enabled, VCC = 5V | 270 | |
| Power-down current WDT disabled 3V | ICC | 0.8 | 40 | µA | Power-down mode, WDT disabled, VCC = 3V | 270 | |
| Power-down current WDT disabled 5V | ICC | 1.1 | 60 | µA | Power-down mode, WDT disabled, VCC = 5V | 270 | |
| Calibrated internal RC oscillator accuracy (factory, 3V) | -1 | 1 | % | 8.0MHz, 3V, 25°C | 271 | ||
| Calibrated internal RC oscillator accuracy (2.7-5.5V) | -14 | 14 | % | 8.0MHz, VCC 2.7V to 5.5V, -40°C to 125°C | 271 | ||
| Calibrated internal RC oscillator accuracy (factory, 5V) | -1 | 1 | % | 8.0MHz, 5V, 25°C | 271 | ||
| Calibrated internal RC oscillator accuracy (4.5-5.5V) | -10 | 10 | % | 8.0MHz, VCC 4.5V to 5.5V, -40°C to 125°C | 271 | ||
| Watchdog oscillator accuracy | -40 | 40 | % | 128kHz, VCC 2.7V to 5.5V, -40°C to 125°C | 271 | ||
| Oscillator frequency (external clock, 2.7-5.5V) | 1/tCLCL | 0 | 8 | MHz | VCC = 2.7 - 5.5V | 271 | |
| Oscillator frequency (external clock, 4.5-5.5V) | 1/tCLCL | 0 | 16 | MHz | VCC = 4.5 - 5.5V | 271 | |
| Bandgap reference voltage | VBG | 1 | 1.1 | 1.2 | V | 272 | |
| Power-on reset threshold voltage (falling) | VPOT | 0.6 | 1.3 | 1.6 | V | 272 | |
| BOD trigger level VBOT (BODLEVEL 110) | VBOT | 1.6 | 1.8 | 2 | V | BODLEVEL 2:0 = 110 | 272 |
| BOD trigger level VBOT (BODLEVEL 101) | VBOT | 2.5 | 2.7 | 2.9 | V | BODLEVEL 2:0 = 101 | 272 |
| BOD trigger level VBOT (BODLEVEL 100) | VBOT | 3.9 | 4.3 | 4.6 | V | BODLEVEL 2:0 = 100 | 272 |
| Output low voltage two-wire bus | VOL | 0 | 0.4 | V | 3mA sink current | 275 | |
| Input current each I/O pin two-wire bus | Ii | -10 | 10 | µA | 0.1VCC < Vi < 0.9VCC | 275 | |
| SCL clock frequency | fSCL | 0 | 400 | kHz | fCK > max(16fSCL, 250kHz) | 275 | |
| ADC resolution | 10 | Bits | -40°C to 125°C, 2.70V to 5.50V, ADC clock = 200kHz | 276 | |||
| ADC absolute accuracy TUE | TUE | 2.2 | 3.5 | LSB | VCC = 4V, VREF = 4V | 276 | |
| ADC integral non-linearity | INL | 0.6 | 1.5 | LSB | VCC = 4V, VREF = 4V | 276 | |
| ADC differential non-linearity | DNL | 0.3 | 0.7 | LSB | VCC = 4V, VREF = 4V | 276 | |
| ADC gain error | -4 | 3 | LSB | VCC = 4V, VREF = 4V | 276 | ||
| ADC offset error | -3.5 | 3.5 | LSB | VCC = 4V, VREF = 4V | 276 | ||
| ADC clock frequency | 50 | 200 | kHz | 276 | |||
| Internal voltage reference VINT | VINT | 1 | 1.1 | 1.2 | V | 276 | |
| Reference input resistance | RREF | 22 | 32 | 42 | k | 276 |
CAD (KiCad official)
- Symbol:
ATMEGA168PA-MU - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
atmega168pa-mu-etched.step/atmega168pa-mu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atmega168pa-mu.step/atmega168pa-mu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (326 pp, sha256
626d81e6d4d566ae, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATMEGA168PA-MU
**Microchip Tech** · MICROCHIP · VQFN-32-EP(5x5)
ATMEGA168PA-MU from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD3/INT1/OC2B/PCINT19 | bidirectional | Port D bit 3 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as external interrupt 1 input and OC2B output. |
| 2 | PD4/XCK/T0/PCINT20 | bidirectional | Port D bit 4 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as USART external clock XCK and Timer/Counter0 input T0. |
| 3 | GND | power_in | Ground reference for the digital supply. |
| 4 | VCC | power_in | Digital supply voltage; the operating range is 2.7V to 5.5V. |
| 5 | GND | power_in | Ground reference for the digital supply. |
| 6 | VCC | power_in | Digital supply voltage; the operating range is 2.7V to 5.5V. |
| 7 | PB6/XTAL1/TOSC1/PCINT6 | bidirectional | Port B bit 6 serves as the chip clock oscillator input XTAL1 or timer oscillator TOSC1 depending on the clock fuse settings, and cannot be used as I/O when used as a clock pin. |
| 8 | PB7/XTAL2/TOSC2/PCINT7 | bidirectional | Port B bit 7 serves as the inverting oscillator amplifier output XTAL2 or timer oscillator TOSC2 depending on the clock fuse settings, and cannot be used as I/O when used as a clock pin. |
| 9 | PD5/T1/OC0B/PCINT21 | bidirectional | Port D bit 5 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as Timer/Counter1 external counter input T1 and OC0B output. |
| 10 | PD6/AIN0/OC0A/PCINT22 | bidirectional | Port D bit 6 is a bidirectional I/O pin that serves as analog comparator positive input AIN0 (pull-up should be off in that use) and OC0A output. |
| 11 | PD7/AIN1/PCINT23 | bidirectional | Port D bit 7 is a bidirectional I/O pin that serves as analog comparator negative input AIN1 (pull-up should be off in that use). |
| 12 | PB0/ICP1/CLKO/PCINT0 | bidirectional | Port B bit 0 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as Timer/Counter1 input capture ICP1 and divided clock output CLKO. |
| 13 | PB1/OC1A/PCINT1 | bidirectional | Port B bit 1 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as Timer/Counter1 output compare A output OC1A. |
| 14 | PB2/SS/OC1B/PCINT2 | bidirectional | Port B bit 2 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI slave select SS and Timer/Counter1 output compare B output OC1B. |
| 15 | PB3/MOSI/OC2A/PCINT3 | bidirectional | Port B bit 3 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI MOSI and Timer/Counter2 output compare A output OC2A. |
| 16 | PB4/MISO/PCINT4 | bidirectional | Port B bit 4 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI master input/slave output MISO. |
| 17 | PB5/SCK/PCINT5 | bidirectional | Port B bit 5 is a bidirectional I/O pin with internal pull-up that is tri-stated on reset, also serving as SPI clock SCK. |
| 18 | AVCC | power_in | Supply voltage pin for the A/D converter, PC3:0 and ADC7:6, which should be connected to VCC even if the ADC is not used. |
| 19 | ADC6 | input | Analog input channel 6 of the 10-bit A/D converter, powered from the analog supply (TQFP and QFN package only). |
| 20 | AREF | input | Analog reference pin for the A/D converter. |
| 21 | GND | power_in | Ground reference for the digital supply. |
| 22 | ADC7 | input | Analog input channel 7 of the 10-bit A/D converter, powered from the analog supply (TQFP and QFN package only). |
| 23 | PC0/ADC0/PCINT8 | bidirectional | Port C bit 0 is a 7-bit port pin that is tri-stated on reset, also serving as ADC input channel 0 using analog power. |
| 24 | PC1/ADC1/PCINT9 | bidirectional | Port C bit 1 is a port pin that is tri-stated on reset, also serving as ADC input channel 1 using analog power. |
| 25 | PC2/ADC2/PCINT10 | bidirectional | Port C bit 2 is a port pin that is tri-stated on reset, also serving as ADC input channel 2 using analog power. |
| 26 | PC3/ADC3/PCINT11 | bidirectional | Port C bit 3 is a port pin that is tri-stated on reset, also serving as ADC input channel 3 using analog power. |
| 27 | PC4/ADC4/SDA/PCINT12 | bidirectional | Port C bit 4 is a port pin that is tri-stated on reset, also serving as 2-wire serial data SDA and ADC input channel 4 using digital power. |
| 28 | PC5/ADC5/SCL/PCINT13 | bidirectional | Port C bit 5 is a port pin that is tri-stated on reset, also serving as 2-wire serial clock SCL and ADC input channel 5 using digital power. |
| 29 | PC6/RESET/PCINT14 | input | When the RSTDISBL fuse is unprogrammed this pin is an active-low reset input, and a low level longer than the minimum pulse length generates a reset; when programmed it acts as I/O with electrical characteristics differing from other port C pins. |
| 30 | PD0/RXD/PCINT16 | bidirectional | Port D bit 0 is a bidirectional I/O pin that serves as USART receive data input RXD when the USART receiver is enabled. |
| 31 | PD1/TXD/PCINT17 | bidirectional | Port D bit 1 is a bidirectional I/O pin that serves as USART transmit data output TXD and is configured as an output whenever the USART transmitter is enabled. |
| 32 | PD2/INT0/PCINT18 | bidirectional | Port D bit 2 is a bidirectional I/O pin that serves as external interrupt source 0 INT0. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature | | -55 | | 125 | °C | | 268 |
| Storage temperature | | -65 | | 150 | °C | | 268 |
| Voltage on any pin except RESET with respect to ground | | -0.5 | | | V | | 268 |
| Voltage on RESET with respect to ground | | -0.5 | | 13 | V | | 268 |
| Maximum operating voltage | | | | 6 | V | | 268 |
| DC current per I/O pin | | | | 40 | mA | | 268 |
| DC current VCC and GND pins | | | | 200 | mA | | 268 |
| Supply voltage | VCC | 2.7 | | 5.5 | V | TA = -40°C to 125°C | 269 |
| Input leakage current I/O pin (low) | IIL | | | 1 | µA | VCC = 5.5V, pin low (absolute value) | 269 |
| Input leakage current I/O pin (high) | IIH | | | 1 | µA | VCC = 5.5V, pin high (absolute value) | 269 |
| Reset pull-up resistor | RRST | 30 | | 60 | k | VCC = 5V, Vin = 0V | 269 |
| I/O pin pull-up resistor | RPU | 20 | | 50 | k | | 269 |
| Analog comparator input offset voltage | VACIO | | | 40 | mV | VCC = 5V, 0.1VCC < Vin < VCC - 100mV | 269 |
| Analog comparator input leakage current | IACLK | -50 | | 50 | nA | 0.1VCC < Vin < VCC, 100mV | 269 |
| Output low voltage except RESET pin (20mA) | VOL | | | 0.8 | V | IOL = 20mA, VCC = 5V | 269 |
| Output low voltage except RESET pin (5mA) | VOL | | | 0.5 | V | IOL = 5mA, VCC = 3V | 269 |
| Output high voltage except reset pin (20mA) | VOH | 4.1 | | | V | IOH = -20mA, VCC = 5V | 269 |
| Output high voltage except reset pin (10mA) | VOH | 2.3 | | | V | IOH = -10mA, VCC = 3V | 269 |
| Active supply current 4MHz | ICC | | 1.3 | 2.4 | mA | Active 4MHz, VCC = 3V | 270 |
| Active supply current 8MHz | ICC | | 4.6 | 10 | mA | Active 8MHz, VCC = 5V | 270 |
| Active supply current 16MHz | ICC | | 8.4 | 16 | mA | Active 16MHz, VCC = 5V | 270 |
| Idle supply current 4MHz | ICC | | 0.2 | 0.6 | mA | Idle 4MHz, VCC = 3V | 270 |
| Idle supply current 8MHz | ICC | | 0.9 | 1.6 | mA | Idle 8MHz, VCC = 5V | 270 |
| Idle supply current 16MHz | ICC | | 1.8 | 4 | mA | Idle 16MHz, VCC = 5V | 270 |
| Power-down current WDT enabled 3V | ICC | | 4.2 | 44 | µA | Power-down mode, WDT enabled, VCC = 3V | 270 |
| Power-down current WDT enabled 5V | ICC | | 6.2 | 66 | µA | Power-down mode, WDT enabled, VCC = 5V | 270 |
| Power-down current WDT disabled 3V | ICC | | 0.8 | 40 | µA | Power-down mode, WDT disabled, VCC = 3V | 270 |
| Power-down current WDT disabled 5V | ICC | | 1.1 | 60 | µA | Power-down mode, WDT disabled, VCC = 5V | 270 |
| Calibrated internal RC oscillator accuracy (factory, 3V) | | -1 | | 1 | % | 8.0MHz, 3V, 25°C | 271 |
| Calibrated internal RC oscillator accuracy (2.7-5.5V) | | -14 | | 14 | % | 8.0MHz, VCC 2.7V to 5.5V, -40°C to 125°C | 271 |
| Calibrated internal RC oscillator accuracy (factory, 5V) | | -1 | | 1 | % | 8.0MHz, 5V, 25°C | 271 |
| Calibrated internal RC oscillator accuracy (4.5-5.5V) | | -10 | | 10 | % | 8.0MHz, VCC 4.5V to 5.5V, -40°C to 125°C | 271 |
| Watchdog oscillator accuracy | | -40 | | 40 | % | 128kHz, VCC 2.7V to 5.5V, -40°C to 125°C | 271 |
| Oscillator frequency (external clock, 2.7-5.5V) | 1/tCLCL | 0 | | 8 | MHz | VCC = 2.7 - 5.5V | 271 |
| Oscillator frequency (external clock, 4.5-5.5V) | 1/tCLCL | 0 | | 16 | MHz | VCC = 4.5 - 5.5V | 271 |
| Bandgap reference voltage | VBG | 1 | 1.1 | 1.2 | V | | 272 |
| Power-on reset threshold voltage (falling) | VPOT | 0.6 | 1.3 | 1.6 | V | | 272 |
| BOD trigger level VBOT (BODLEVEL 110) | VBOT | 1.6 | 1.8 | 2 | V | BODLEVEL 2:0 = 110 | 272 |
| BOD trigger level VBOT (BODLEVEL 101) | VBOT | 2.5 | 2.7 | 2.9 | V | BODLEVEL 2:0 = 101 | 272 |
| BOD trigger level VBOT (BODLEVEL 100) | VBOT | 3.9 | 4.3 | 4.6 | V | BODLEVEL 2:0 = 100 | 272 |
| Output low voltage two-wire bus | VOL | 0 | | 0.4 | V | 3mA sink current | 275 |
| Input current each I/O pin two-wire bus | Ii | -10 | | 10 | µA | 0.1VCC < Vi < 0.9VCC | 275 |
| SCL clock frequency | fSCL | 0 | | 400 | kHz | fCK > max(16fSCL, 250kHz) | 275 |
| ADC resolution | | | 10 | | Bits | -40°C to 125°C, 2.70V to 5.50V, ADC clock = 200kHz | 276 |
| ADC absolute accuracy TUE | TUE | | 2.2 | 3.5 | LSB | VCC = 4V, VREF = 4V | 276 |
| ADC integral non-linearity | INL | | 0.6 | 1.5 | LSB | VCC = 4V, VREF = 4V | 276 |
| ADC differential non-linearity | DNL | | 0.3 | 0.7 | LSB | VCC = 4V, VREF = 4V | 276 |
| ADC gain error | | -4 | | 3 | LSB | VCC = 4V, VREF = 4V | 276 |
| ADC offset error | | -3.5 | | 3.5 | LSB | VCC = 4V, VREF = 4V | 276 |
| ADC clock frequency | | 50 | | 200 | kHz | | 276 |
| Internal voltage reference VINT | VINT | 1 | 1.1 | 1.2 | V | | 276 |
| Reference input resistance | RREF | 22 | 32 | 42 | k | | 276 |
## CAD (KiCad official)
- Symbol: `ATMEGA168PA-MU`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `atmega168pa-mu-etched.step` / `atmega168pa-mu-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atmega168pa-mu.step` / `atmega168pa-mu.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/Atmel-9223-Automotive-Microcontrollers-ATmega48PA-ATmega88PA-ATmega168PA_Datasheet.pdf) (326 pp, sha256 `626d81e6d4d566ae`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/atmega168pa-mu-datasheet.pdf)